Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage

• Published in: IEEE journal of solid-state circuits Vol. 37; no. 11; pp. 1396 - 1402
• Main Authors: Tschanz, J.W., Kao, J.T., Narendra, S.G., Nair, R., Antoniadis, D.A., Chandrakasan, A.P., De, V.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-11-2002; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Acceptance tests; Bias; Circuits; Clocks; CMOS; CMOS digital integrated circuits; Costs; Electric potential; Energy consumption; Frequency measurement; Microprocessors; MOS devices; Optimization; Process design; Testing; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2002.803949

Bidirectional adaptive body bias (ABB) is used to compensate for die-to-die parameter variations by applying an optimum pMOS and nMOS body bias voltage to each die which maximizes the die frequency subject to a power constraint. Measurements on a 150 nm CMOS test chip which incorporates on-chip ABB, show that ABB reduces variation in die frequency by a factor of seven, while improving the die acceptance rate. An enhancement of this technique, that compensates for within-die parameter variations as well, increases the number of dies accepted in the highest frequency bin. ABB is therefore shown to provide bin split improvement in the presence of increasing process parameter variations.