A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

• Published in: IEEE journal of solid-state circuits Vol. 43; no. 4; pp. 919 - 928
• Main Authors: Park, Ki-Tae, Kang, Myounggon, Kim, Doogon, Hwang, Soon-Wook, Choi, Byung Yong, Lee, Yeong-Taek, Kim, Changhyun, Kim, Kinam
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01-04-2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Architecture; Arrays; Background noise; Bitline voltage modulation ISPP; cell-to-cell interference; Circuit properties; Costs; Design. Technologies. Operation analysis. Testing; Digital cameras; Digital circuits; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Flash memory; Flash memory (computers); Integrated circuits; Integrated circuits by function (including memories and processors); Interference; Magnetic and optical mass memories; Modulation coding; NAND flash; Offset printing; page architecture; parallel MSB programming; Parallel programming; Programming; Semiconductor device noise; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Service oriented architecture; Storage; Storage and reproduction of information; temporary LSB storing; Voltage; Performance evaluation; cell-to-cell interference; Memory devices; NAND circuit; Bitline voltage modulation ISPP; page architecture; Logic circuit; Parallel programming; Flash memory; NAND flash; temporary LSB storing; Integrated circuit; Parallel program; parallel MSB programming
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2008.917558

A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel page architecture including temporary LSB storing program and parallel MSB program schemes is proposed. A BL voltage modulated ISPP scheme was used as parallel MSB programming in order to reduce cell-to-cell interference caused by the order in which the cells are programmed. By adopting the proposed page architecture, the number of neighbor cells that are programmed after programming a selected cell in BL direction as well as their amount of T/th shift during programming can be suppressed largely without increasing memory array size. Compared to conventional architecture it leads to a reduction of BL-BL cell-to-cell interference by almost 100%, and of WL-WL and diagonal cell-to-cell interferences by 50% at the 60 nm technology node. The proposed architecture enables also to improve average MLC program speed performance by 11% compared with conventional architecture, thanks to its fast LSB program performance.