A simple technology for superjunction device fabrication: polyflanked VDMOSFET

• Published in: IEEE electron device letters Vol. 23; no. 10; pp. 627 - 629
• Main Authors: Kian Paau Gan, Xin Yang, Liang, Y.C., Samudra, G.S., Liu Yong
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-10-2002; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Breakdown voltage; Charge; Cost engineering; Costs; Devices; Doping; Fabrication; Gallium nitride; Gallium nitrides; Metal oxide semiconductors; MOS devices; MOSFET circuits; MOSFETs; Power MOSFET; Production; Silicon
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2002.803770

The charge compensation based novel superjunction (SJ) MOSFET outperforms its conventional counterparts. However, the production of SJ devices is limited by a complicated and costly fabrication process. In this letter, a feasible technology for polyflanked vertical double-diffused MOS SJ structure, as in Gan et al. (2001), is introduced and demonstrated to have greatly reduced fabrication costs, simplified processes, and overcome the interdiffusion problem of SJ columns. This brings forth the new milestone that SJ MOS devices can now be fabricated by standard cleanroom facilities.