Physics-based stability analysis of MOS transistors

• Published in: Solid-state electronics Vol. 113; pp. 28 - 34
• Main Authors: Ferrara, A., Steeneken, P.G., Boksteen, B.K., Heringa, A., Scholten, A.J., Schmitz, J., Hueting, R.J.E.
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01-11-2015
• Subjects: Failure function; Power MOSFET; Safe Operating Area (SOA); Safe Operating Volume (SOV); Silicon-on-insulator (SOI); Stability factor; Silicon-on-insulator (SOI); Safe Operating Area (SOA); Stability factor; Power MOSFET; Failure function; Safe Operating Volume (SOV)
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/j.sse.2015.05.010

In this work, a physics-based model is derived based on a linearization procedure for investigating the electrical, thermal and electro-thermal instability of power metal–oxide–semiconductor (MOS) transistors. The proposed model can be easily interfaced with a circuit or device simulator to perform a failure analysis, making it particularly useful for power transistors. Furthermore, it allows mapping the failure points on a three-dimensional (3D) space defined by the gate-width normalized drain current, drain voltage and junction temperature. This leads to the definition of the Safe Operating Volume (SOV), a powerful frame work for making failure predictions and determining the main root of instability (electrical, thermal or electro-thermal) in different bias and operating conditions. A comparison between the modeled and the measured SOV of silicon-on-insulator (SOI) LDMOS transistors is reported to support the validity of the proposed stability analysis.