Overhang Saddle Fin Sidewall Structure for Highly Reliable DRAM Operation

• Published in: IEEE access Vol. 11; pp. 82738 - 82743
• Main Authors: Han, Jin-Woo, Suh, Minki, Lee, Gyeongyeop, Kim, Jungsik
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CAD; Capacitors; Computer aided design; Design automation; DRAM; DRAM chips; Dynamic random access memory; Electric fields; Electric potential; Etching; Leakage current; Logic gates; Overhang saddle fin; Programming; Random access memory; Reliability; retention time; rowhammer; Simulation; TCAD simulation
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2023.3300443

A novel memory cell transistor structure based on a saddle fin-based DRAM is presented for highly reliable operations. The overhang saddle fin (oss-fin) active structure is formed by two steps of etching of the fin; isotropic etching for the short side and anisotropic etching for the long side of the fin. The overhang sidewall fin structure results in the increase of retention time, decrease of isolation leakage current, increase of rowhammering tolerance, and increase of programming efficiency. A Technology Computer-Aided Design (TCAD) simulation study compares the overhang and the conventional saddle fin (s-fin) in terms of those reliability parameters. A lowered electric field underneath the storage node, a lowered passing gate coupling capacitance, and an elongated isolation leakage path are attributed to the reliability enhancements in the overhang saddle fin.