A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI

• Published in: IEEE journal of solid-state circuits Vol. 45; no. 7; pp. 1286 - 1294
• Main Authors: Siligaris, Alexandre, Hamada, Yasuhiro, Mounet, Christopher, Raynaud, Christine, Martineau, Baudouin, Deparis, Nicolas, Rolland, Nathalie, Fukaishi, Muneo, Vincent, Pierre
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-07-2010; The Institute of Electrical and Electronics Engineers, Inc. (IEEE); Institute of Electrical and Electronics Engineers
• Subjects: 60 GHz; Broadband amplifiers; Circuits; CMOS; CMOS process; Coplanar transmission lines; Coplanar waveguides; CPW; Electric potential; Impedance matching; power amplifier; Power amplifiers; Power measurement; Power transmission lines; Propagation losses; Saturation; SOI; Transmission line measurements; V-band; Voltage; Wideband
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2010.2049456

A 60 GHz wideband power amplifier (PA) is fabricated in a standard CMOS SOI 65 nm process. The PA is based on two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high-resistivity SOI substrate (3 kΩ · cm). The PA measurements are carried out for supply voltages V DD going from 1.2 V to 2.6 V and achieve a saturation power of 10 dBm to 16.5 dBm respectively. The peak power-added efficiency (PAE) is higher than 20% for all applied V DD values.