Efficient Homomorphic Encryption Accelerator With Integrated PRNG Using Low-Cost FPGA

• Published in: IEEE access Vol. 10; pp. 7753 - 7771
• Main Authors: Syafalni, Infall, Jonatan, Gilbert, Sutisna, Nana, Mulyawan, Rahmat, Adiono, Trio
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: BFV scheme; Cloud computing; Computer memory; Convolution; Cryptography; Cybersecurity; Data privacy; Encryption; fully homomorphic encryption; Gaussian PRNG; hardware accelerator; Homomorphic encryption; Mathematical analysis; Microprocessors; Multiplication; Noise generation; Polynomials; Privacy; Pseudorandom; Random noise; Random numbers; Rings (mathematics); Software; Subtraction; systolic array; Systolic arrays
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2022.3143804

With recent development in internet speed and reliability, cloud computing has become a more reliable solution for the user. In many cases where data privacy is critical, fully homomorphic encryption (FHE) can be a security solution for securing cloud computing. FHE enables computation on encrypted data, hence it ensures data privacy in case of cloud computing. One popular scheme of FHE is the BFV homomorphic encryption scheme, which is based on ring learning with error (RLWE) computation. The BFV scheme uses ring polynomials as the main object, hence its encryption, decryption, and evaluation require high-degree polynomial multiplication. In this paper, we present comprehensive design and implementation of a hardware architecture to accelerate encryption and decryption in BFV scheme. Our accelerator uses convolution approach for calculating a polynomial multiplication. To implement the convolution, we use a systolic array to calculate polynomial convolution followed by a simple delayed subtraction to calculate polynomial modulo reduction inside our accelerator's core. Moreover, we use a built-in Gaussian pseudo-random number generator (PRNG) to generate Gaussian noise in the encryption operations. Finally, we implement the 1024 degrees BFV accelerator on the Xilinx PYNQ Z1 board and compare the encryption and decryption performances to other methods as well as a software implementation on Intel Core i7 with 8GB memory. Experimental results show that our accelerator outperforms the clock cycles of other methods with the same polynomial degrees 1024 up to <inline-formula> <tex-math notation="LaTeX">22\times </tex-math></inline-formula>. Moreover, our proposed Gaussian PRNG has better <inline-formula> <tex-math notation="LaTeX">2\times </tex-math></inline-formula> correlation compared to the rotation-only-based PRNG. Finally, our accelerator accelerates up to <inline-formula> <tex-math notation="LaTeX">9\times </tex-math></inline-formula> for encryption and <inline-formula> <tex-math notation="LaTeX">3.5\times </tex-math></inline-formula> for decryption as well as <inline-formula> <tex-math notation="LaTeX">6.8\times </tex-math></inline-formula> for overall compared to Microsoft SEAL on Intel Core i7 processor with 8GB memory. The proposed design is scalable for higher degrees polynomial multiplication and useful for security technology such as high-speed secure cloud computing, blind computing, and secure communication.