Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer

• Published in: IEEE access Vol. 8; p. 1
• Main Authors: Choi, Ji-Min, Yoon, Dong-Hyun, Jung, Dong-Kyu, Seong, Kiho, Han, Jae-Soub, Lee, Woojoo, Baek, Kwang-Hyun
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01-01-2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuits; Decoding; Degradation; Direct digital frequency synthesizer (DDFS/DDS); Dithering; Dithering scheme; Finite wordlength effects; Frequency control; Frequency synthesizers; High spurious-free dynamic range (SFDR); Low power design; Performance degradation; Phase accumulator (PACC); Portable equipment; Power consumption; Power demand; Power efficiency; Power management; Pseudo-random binary sequence (PRBS); Read only memory; Side effects; Truncation errors
• ISSN: 2169-3536; 2169-3536
• DOI: 10.1109/ACCESS.2020.2986016

Due to the advantages of fast frequency shifting, continuous phase shifting, fine frequency resolution, large bandwidth, and excellent spectral purity, the direct digital frequency synthesis (DDFS) technique is attracting more attention than ever before. Although the DDFS suffer from high power consumption, recent researches on the development of the low power DDFS (LP-DDFS) increases the feasibility of applying the DDFS to portable devices. To further accelerate the use of LP-DDFS, a new LP-DDFS design to significantly improve power efficiency is proposed and analyzed in this paper. In the new design, the dominant spur by truncation errors causing performance degradation has been also thoroughly considered. Since the existing dithering techniques for the truncation error problems can cause the additional performance degradation due to the side effects such as frequency offset and SNDR deterioration, an enhanced dithering technique is also proposed in this paper. The proposed technique includes a frequency compensation circuit and thus minimizes the truncation errors in the LP-DDFS with the minimal additional power consumption and SNDR degradation. Both theoretical and experimental analysis are conducted to verify the proposed design, where a prototype chip is fabricated and measured.