Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 55; no. 10; pp. 986 - 990
• Main Authors: Do Anh-Tuan, Kong Zhi-Hui, Yeo Kiat-Seng
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-10-2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Delay; Differential amplifiers; Energy consumption; High power amplifiers; High speed; Integrated circuit technology; Low-power SRAM; low-voltage SRAM; Parasitic capacitance; Power engineering and energy; Random access memory; Reliability engineering; Robustness; Semiconductor devices; sense amplifier (SA); Sense amplifiers; Sizing; Static random access memory; Transistors; Voltage
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2008.2001965

A novel high-speed sense amplifier for ultra-low-voltage SRAM applications is presented. It introduces a completely different way of sizing the aspect ratio of the transistors on the data-path, hence realizing a current-voltage hybrid mode Sense Amplifier. Extensive post-layout simulations have proved that the new Sense Amplifier provides both high-speed and low-power properties, with its delay and power reduced to 25.8% and 37.6% of those of the best prior art. It also offers a much better read-effectiveness and robustness against the bit- and data-line capacitances as well as V DD variations. Furthermore, the new Sense Amplifier is able to tolerate a large difference between the parasitic capacitances associated with the complementary DLs. It can operate down to a supply voltage of 0.9 V, the lowest reported for a 0.18 mum CMOS process. A modified cross-coupled amplifier is also introduced, allowing the Sense Amplifier to operate down to 0.55 V.