System-level Pareto frontiers for on-chip thermoelectric coolers

• Published in: Frontiers in Energy Vol. 12; no. 1; pp. 109 - 120
• Main Authors: U. YURUKER, Sevket, C. FISH, Michael, YANG, Zhi, BALDASARO, Nicholas, BARLETTA, Philip, BAR-COHEN, Avram, YANG, Bao
• Format: Journal Article
• Language: English
• Published: Beijing Higher Education Press 01-03-2018; Springer Nature B.V
• Subjects: Architecture; Circuit reliability; Coolers; Cooling; Electric currents; Energy; Energy Systems; Finite element method; Heat; Heat flux; Heat transfer; high flux electronics; Integrated circuits; Mathematical models; Optimization; Pareto;系统可靠性;冷却器;热电;薄片;有限元素分析;优化过程;体系结构; Research Article; System reliability; Temperature effects; thermal management; Thermoelectric cooling; optimization; thermal management; high flux electronics; thermoelectric cooling
• ISSN: 2095-1701; 2095-1698
• DOI: 10.1007/s11708-018-0540-8

The continuous rise in heat dissipation of integrated circuits necessitates advanced thermal solutions to ensure system reliability and efficiency. Thermoelectric coolers are among the most promising techniques for dealing with localized on-chip hot spots. This study focuses on establishing a holistic optimization methodol- ogy for such thermoelectric coolers, in which a thermo- electric element＇s thickness and the electrical current are optimized to minimize source temperature with respect to ambient, when the thermal and electrical parasitic effects are considered. It is found that when element thickness and electrical current are optimized for a given system architecture, a ＂heat flux vs. temperature difference＂ Pareto frontier curve is obtained, indicating that there is an optimum thickness and a corresponding optimum current that maximize the achievable temperature reduc- tion while removing a particular heat flux. This methodol- ogy also provides the possible system level AT＇s that can be achieved for a range of heat fluxes, defining the upper limits of thermoelectric cooling for that architecture. In this study, use was made of an extensive analytical model, which was verified using commercially available finite element analysis software. Through the optimization process, 3 pairs of master curves were generated, which were then used to compose the Pareto frontier for any given system architecture. Finally, a case study wasperformed to provide an in-depth demonstration of the optimization procedure for an example application.