Architecture and Finite Precision Optimization for Layered LDPC Decoders

• Published in: Journal of signal processing systems Vol. 65; no. 2; pp. 185 - 197
• Main Authors: Marchand, Cédric, Conde-Canencia, Laura, Boutillon, Emmanuel
• Format: Journal Article
• Language: English
• Published: Boston Springer US 01-11-2011; Springer
• Subjects: Architecture; Channels; Circuits and Systems; Computer Imaging; Computer Science; Decoders; Electrical Engineering; Engineering; Engineering Sciences; Image Processing and Computer Vision; Messages; Optimization; Pattern Recognition; Pattern Recognition and Graphics; Quantization; Signal and Image processing; Signal processing; Signal,Image and Speech Processing; Vision; DVB-S2; Layered decoding; Low-density parity-check (LDPC) code; VLSI implementation
• ISSN: 1939-8018; 1939-8115
• DOI: 10.1007/s11265-011-0604-z

Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, two main issues affect performance and area of practical implementations: quantization and memory. Quantization can strongly degrade performance and memory area can constitute up to 70% of the total area of the decoder implementation. This is the case of the DVB-S2,-T2 and -C2 decoders when considering long frames. This paper is then dedicated to the optimization of these decoders. We first focus on the reduction of the number of quantization bits and propose solutions based on the efficient saturation of the channel values, the extrinsic messages and the a posteriori probabilities (APP). We reduce from 6 to 5 the number of quantization bits for the channel and the extrinsic messages and from 8 to 6 the APPs, without introducing any performance loss. We then consider the optimization of the size of the extrinsic memory considering a multiple code rates decoder. The paper finally presents an optimized fixed-point architecture of a DVB-S2 layered decoder and its implementation on an FPGA device.