On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform

• Published in: IEEE transactions on circuits and systems for video technology Vol. 17; no. 7; pp. 814 - 822
• Main Authors: CHENG, Chih-Chi, HUANG, Chao-Tsung, CHEN, Ching-Yeh, LIAN, Chung-Jr, CHEN, Liang-Gee
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-07-2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Bandwidth; Buffers; Circuits; Coding, codes; Computer buffers; Design. Technologies. Operation analysis. Testing; Discrete Wavelet Transform; Discrete wavelet transform (DWT); Discrete wavelet transforms; Electronics; Exact sciences and technology; Filters; Hardware; Image coding; image compression; Information, signal and communications theory; Integrated circuits; Integrated circuits by function (including memories and processors); JPEG 2000; Methodology; Miscellaneous; MPEG 4 Standard; MPEG-4; Noise levels; Optimization; Registers; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal and communications theory; Signal processing; Telecommunications and information theory; Transform coding; Very large scale integration; VLSI architecture; Overflow(computer arithmetics); JPEG 2000; MPEG-4; Signal compression; Discrete wavelet transform (DWT); VLSI circuit; Image processing; Data compression; Discrete transformation; Image compression; VLSI architecture; Buffer system; Discrete wavelet transforms; Implementation; Optimization; Circuit architecture; Image coding; Wavelet transformation; Storage management; Integrated circuit; Signal processing; Signal to noise ratio
• ISSN: 1051-8215; 1558-2205
• DOI: 10.1109/TCSVT.2007.897106

The on-chip line buffer dominates the total area and power of line-based 2-D discrete wavelet transform (DWT). In this paper, a memory-efficient VLSI implementation scheme for line-based 2-D DWT is proposed, which consists of two parts, the wordlength analysis methodology and the multiple-lifting scheme. The required wordlength of on-chip memory is determined firstly by use of the proposed wordlength analysis methodology, and a memory-efficient VLSI implementation scheme for line-based 2-D DWT, named multiple-lifting scheme, is then proposed. The proposed wordlength analysis methodology can guarantee to avoid overflow of coefficients, and the average difference between predicted and experimental quality level is only 0.1 dB in terms of PSNR. The proposed multiple-lifting scheme can reduce not only at least 50% on-chip memory bandwidth but also about 50% area of line buffer in 2-D DWT module.