Application of the surface planer process to Cu pillars and wafer support tape for high-coplanarity wafer-level packaging

• Published in: International journal of advanced manufacturing technology Vol. 119; no. 5-6; pp. 3427 - 3435
• Main Authors: Inoue, Fumihiro, Phommahaxay, Alain, Gokita, Yohei, Möller, Berthold, Beyne, Eric
• Format: Journal Article
• Language: English
• Published: London Springer London 01-03-2022; Springer Nature B.V
• Subjects: Advanced manufacturing technologies; CAE) and Design; Computer-Aided Engineering (CAD; Coplanarity; Electronic packaging; Engineering; Grinding tools; Industrial and Production Engineering; Manufacturing; Mechanical Engineering; Media Management; Nonuniformity; Original Article; Plating; Thickness; Topography; Cu pillar; Packaging electronics; Backgrind tape; Surface planer; Grinding
• ISSN: 0268-3768; 1433-3015
• DOI: 10.1007/s00170-021-08622-x

We used the surface planer process to minimize the within-die and within-wafer nonuniformity caused by the nonoptimized Cu pillar and Si thinning processes. The height variation of the planarized Cu pillars was 3.5% of the within-wafer uniformity in a 300-mm wafer, which represents a substantial reduction of the post-electrodeposition height variation. In addition, the topography of the Cu pillar surface was flat and uniform after the surface planer process. The backgrind tape-laminated Cu pillar wafer exhibited a total thickness variation of 31.77 µm. This variation was reduced to 14.55 µm by the surface planer process. The bulk Si of the Cu pillar wafer with the planarized backgrind tape was thinned to 100 µm by grinding. The total thickness variation of the Si was 1.52 µm when the backgrind tape was subjected to the surface planer process, whereas it was 8.2 µm in the case where the surface planer process was not applied. These results indicate that the surface planer process is a promising method for achieving high coplanarity of a die and wafer, thereby representing an advancement toward high-yield advanced packaging.