An Efficient Hardware Design of the Flexible 2-D System for Space/Spatial-Frequency Signal Analysis

• Published in: IEEE transactions on signal processing Vol. 55; no. 6; pp. 3116 - 3125
• Main Authors: Ivanovic, V.N., Stojanovic, R.D.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-06-2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Clocks; Cost function; Design engineering; Design optimization; Digital signal processor (DSP) system; Energy consumption; Exact sciences and technology; Field programmable gate arrays; field-programmable gate array (FPGA) device; Fourier transforms; Hardware; hardware design; Information, signal and communications theory; Kernel; Kernels; Miscellaneous; multiple clock cycle implementation; Real time; Signal analysis; Signal and communications theory; Signal design; Signal processing; Signal representation. Spectral analysis; Signal, noise; space/spatial-frequency distribution; Telecommunications and information theory; Performance evaluation; multiple clock cycle implementation; Fourier transformation; Digital signal processor (DSP) system; field-programmable gate array (FPGA) device; System design; Field programmable gate array; Clock; Implementation; Kernel method; Spatial frequency; Power consumption; Spatial distribution; Frequency analysis; Information gateway; Signal processing; hardware design; Digital signal processor; space/spatial-frequency distribution; Signal analysis
• ISSN: 1053-587X; 1941-0476
• DOI: 10.1109/TSP.2007.893958

An efficient multiple clock cycle implementation (MCI) of a flexible system for space/spatial-frequency signal analysis is proposed. It is designed by extending the 1-D MCI architecture to the 2-D case. The proposed system can implement various (almost all commonly used) 2-D space/spatial-frequency distributions (S/SFDs) based on the 2-D short-time Fourier transform (STFT) elements. The designed system is very flexible, since it allows the implemented S/SFDs to take different numbers of clock cycles and to share functional kernel, known as the STFT-to-SM gateway, , within their execution. These are major advantages of the MCI approach, that enable one to optimize critical design performances such as hardware complexity, energy consumption, and cost. The proposed approach is verified by a real-time design of the field-programmable gate array chip that is capable of performing 2-D S/SFDs in real time