A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

• Published in: Heliyon Vol. 10; no. 10; p. e31120
• Main Authors: Nishanth Rao, K., Sudha, D., Ibrahim Khalaf, Osamah, Abdulsaheb, Ghaida Muttasher, Kumar, Aruru Sai, Priyanka, S. Siva, Ouahada, Khmaies, Hamam, Habib
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 30-05-2024; Elsevier
• Subjects: Area; Caary skip adder; Carry look ahead adder; CMOS; Delay; Gate diffusion input; PDP; Ripple carry adder; Transmission gate; CMOS; Area; Transmission gate; Carry look ahead adder; Gate diffusion input; PDP; Ripple carry adder; Caary skip adder; Delay
• ISSN: 2405-8440; 2405-8440
• DOI: 10.1016/j.heliyon.2024.e31120

Multipliers are essential components within digital signal processing, arithmetic operations, and various computational tasks, making their design and optimization crucial for improving the efficiency and performance of integrated circuits. Among multiplier architectures, Vedic multipliers stand out due to their inherent efficiency and speed, derived from ancient Indian mathematical principles. This study presents a comprehensive analysis and comparison of 4-bit Vedic multiplier designs utilizing Gate Diffusion Input (GDI), Complementary Metal-Oxide-Semiconductor (CMOS), and Transmission Gate (TG) technologies, utilizing different adder architectures such as Ripple Carry Adder (RCA), and Carry Lookahead Adder (CLA), Carry Skip Adder (CSA). The objective is to explore the performance, area, and power consumption characteristics of these multipliers across different technologies and adder implementations. Each multiplier architecture is meticulously designed and optimized to leverage the unique features of the respective technology while adhering to the principles of Vedic mathematics. The designs are evaluated based on parameters such as transistor count, delay, power dissipation, and area. The results demonstrate the effectiveness of GDI technology in terms of in tems of delay, area, power and PDP when compared with other technologies. The 4-bit Vedic multiplier has been designed using 32 nm technology within Tanner EDA software tools.