Wafer Direct Bonding: From Advanced Substrate Engineering to Future Applications in Micro/Nanoelectronics

• Published in: Proceedings of the IEEE Vol. 94; no. 12; pp. 2060 - 2106
• Main Authors: Christiansen, Silke H., Singh, Rajendra, Gosele, Ulrich
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-12-2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adhesive bonding; Adhesives; Annealing; Applied sciences; Bonded interface; Bonding; bonding energy; Bonding forces; complementary metal-oxide semiconductor (CMOS); Design. Technologies. Operation analysis. Testing; Electronics; Energy measurement; Exact sciences and technology; Fabrication; hybrid substrates; Hydrogen; Integrated circuits; layer transfer; micro-/nano-electro-mechnical systems (M/NEMS); micro/nanoelectronics; Microelectronic fabrication (materials and surfaces technology); Molecular electronics, nanoelectronics; Nanocomposites; Nanoelectronics; Nanomaterials; Nanostructure; Power engineering and energy; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; silicon-on-insulator (SOI); smart cut; strained silicon-on-insulator (sSOI); Temperature; Transistors; twist bonding; Wafer bonding; wafer direct bonding; Wafers; Annealing temperature; Polishing; Nanoelectronics; hybrid substrates; Wafer bonding; Silicon on insulator technology; Microelectronic fabrication; Bonded interface; Three dimensional structure; Complementary MOS technology; layer transfer; micro/nanoelectronics; Delamination; Bonding; micro-/ nano-electro-mechnical systems (M/NEMS); Wafer; wafer direct bonding; High performance; Ion implantation; Annealing; Interface energy; Dielectric materials; Transistor; bonding energy; twist bonding; Adhesion; silicon-on-insulator (SOI); complementary metal-oxide semiconductor (CMOS); Integrated circuit; Mechanical system; strained silicon-on-insulator (sSOl); Nanotechnology; Room temperature; smart cut
• ISSN: 0018-9219; 1558-2256
• DOI: 10.1109/JPROC.2006.886026

Wafer direct bonding refers to the process of adhesion of two flat mirror-polished wafers without using any intermediate gluing layers in ambient air or vacuum at room temperature. The adhesion of the two wafers occurs due to attractive long range van der Waals or hydrogen bonding forces. At room temperature the bonding energy of the interface is low and higher temperature annealing of the bonded wafer pairs has to be carried out to enhance the bonding energy. In this paper, we describe the prerequisites for the wafer-bonding process to occur and the methods to prepare the suitable surfaces for wafer bonding. The characterization techniques to assess the quality of the bonded interfaces and to measure the bonding energy are presented. Next, the applications of wafer direct bonding in the fabrication of novel engineered substrates such as "silicon-on-insulator" and other "on-insulator" substrates are detailed. These novel substrates, often called hybrid substrates, are fabricated using wafer bonding and layer splitting via a high dose hydrogen/helium implantation and subsequent annealing. The specifics of this process, also known as the smart-cut process, are introduced. Finally, the role of wafer bonding in future nanotechnology applications such as nanotransistor fabrication, three-dimensional integration for high-performance micro/nanoelectronics, nanotemplates based on twist bonding, and nano-electro-mechanical systems is discussed