Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

A sensitivity characterization of a Xilinx Artix-7 field programmable gate array (FPGA) against 14.2-MeV neutrons is presented. The content of the internal static random access memories (SRAMs) and flip-flops was downloaded in a PC and compared with a golden version of it. Flipped cells were identif...

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Bibliographic Details
Published in:IEEE transactions on nuclear science Vol. 67; no. 7; pp. 1461 - 1469
Main Authors: Fabero, Juan Carlos, Mecha, Hortensia, Franco, Francisco J., Clemente, Juan Antonio, Korkian, Golnaz, Rey, Solenne, Cheymol, Benjamin, Baylac, Maud, Hubert, Guillaume, Velazco, Raoul
Format: Journal Article
Language:English
Published: New York IEEE 01-07-2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Institute of Electrical and Electronics Engineers
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Summary:A sensitivity characterization of a Xilinx Artix-7 field programmable gate array (FPGA) against 14.2-MeV neutrons is presented. The content of the internal static random access memories (SRAMs) and flip-flops was downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, block RAM (BRAM), or flip-flops. Single bit upsets (SBUs) and multiple cell upsets (MCUs) with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUlti-Scales Single Event Phenomena Predictive Platform (MUSCA SEP3) was used to make assessment of actual environments and an improvement of single event upset (SEU) injection test is proposed.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2020.2977874