Yield Evaluation of 10-kA/cm ^ Nb Multi-Layer Fabrication Process Using Conventional Superconducting RAMs

• Published in: IEEE transactions on applied superconductivity Vol. 17; no. 2; pp. 177 - 180
• Main Authors: Nagasawa, S.., Satoh, T.., Hinode, K.., Kitagawa, Y.., Hidaka, M..
• Format: Journal Article
• Language: English
• Published: IEEE 01-06-2007
• Subjects: Circuits; Fabrication; Insulation; Josephson junctions; Niobium; planarization technique; Process design; random access memories; Random access memory; Read-write memory; reliability; Resistors; superconducting device fabrication; Superconducting epitaxial layers
• ISSN: 1051-8223; 1558-2515
• DOI: 10.1109/TASC.2007.898050

To achieve larger scale and higher speed single flux quantum (SFQ) circuits, we have been developing a 10-kA/cm 2 Nb multi-layer fabrication process composed of more than six pla- narized Nb layers, an Nb/AlO x /Nb junction layer, a Mo resistor layer, and SiO 2 insulator layers. To evaluate reliability of the fabrication process, we have designed superconducting random access memories (RAMs) with four different memory capacities: 256, IK, 4 K, and 16 K bits. Although the circuit configuration of these RAMs is almost the same as that of previously developed ones that have conventional latching devices, we modified the circuit parameters and layout design based on specifications of the new fabrication process. We have obtained operations for the 256-bit RAM with a bit yield of 100%, the lK-bit RAM with a bit yield of 99.8%, and the 4K-bit RAM with a bit yield of 96.7%. The number of defects in the 4K-bit RAM was estimated to be approximately 10. We confirmed that evaluations using the RAMs were effective at detecting defects due to the fabrication process.