Source Line Sensing in Magneto-Electric Random-Access Memory to Reduce Read Disturbance and Improve Sensing Margin
A source line sensing (SLS) scheme is presented, along with a corresponding memory core circuit architecture, for the sensing operation of magneto-electric random-access memory (MeRAM). Compared to a conventional bit-line sensing (BLS) scheme, the proposed SLS, which exploits the voltage-controlled...
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Published in: | IEEE magnetics letters Vol. 7; pp. 1 - 5 |
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Main Authors: | , , , , , , |
Format: | Journal Article |
Language: | English |
Published: |
Piscataway
IEEE
2016
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects: | |
Online Access: | Get full text |
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Summary: | A source line sensing (SLS) scheme is presented, along with a corresponding memory core circuit architecture, for the sensing operation of magneto-electric random-access memory (MeRAM). Compared to a conventional bit-line sensing (BLS) scheme, the proposed SLS, which exploits the voltage-controlled magnetic anisotropy (VCMA) effect, applies a voltage across the magneto-electric tunnel junction (MEJ) with an opposite polarity. The SLS significantly reduces read disturbance and increases the sensing margin due to the enhanced coercivity of the bit during the read operation. Experimental data demonstrate that the thermal stability of nanoscale MEJs increases up to 2 times during the SLS operation compared with conventional BLS. An MEJ compact model based the SLS simulation shows that read disturbance improves by a factor greater than 109 fJ/V·m and the sensing margin increases up to 3 times in the MEJ with the large VCMA coefficient (>100 fJ/V·m). |
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Bibliography: | ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 23 |
ISSN: | 1949-307X 1949-3088 |
DOI: | 10.1109/LMAG.2016.2552149 |