Area‐oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti‐counterfeiting schemes

• Published in: International journal of circuit theory and applications Vol. 45; no. 2; pp. 274 - 291
• Main Authors: Marchand, Cédric, Bossuet, Lilian, Gaj, Kris
• Format: Journal Article
• Language: English
• Published: Bognor Regis Wiley Subscription Services, Inc 01-02-2017; Wiley
• Subjects: Algorithms; area optimization; block ciphers implementation; Computer Science; Cryptography and Security; Electronics; Encryption; Engineering Sciences; Field programmable gate arrays; Hardware; Lightweight; Reduction; Strategy; Weight reduction; lightweight block ciphers; FPGA; hardware implemantations
• ISSN: 0098-9886; 1097-007X
• DOI: 10.1002/cta.2288

Summary
Over the past 10 years, the multitude of highly constrained applications such as radio‐frequency identification and sensor networks has led to a new trend in the development of cryptographic primitives. Many algorithms categorized as lightweight cryptographic algorithms have been developed specifically for these new applications. Comparing them is very important but also very challenging because every application has its own constraints. This fact leads to a different choice of design strategies, and the best algorithm for one application is not necessarily the best for all applications. Moreover, the definition of what is lightweight is not always the same because lightweight covers a reduction in power and energy consumption just as well as a reduction in area for hardware. This article proposes and compares lightweight hardware implementations of four recent block ciphers (Klein, Led, Lilliput, and Ktantan). This work is included in a large project that aims to protect the hardware against cloning and counterfeiting. The main constraint in this field is the area required by the protection scheme. As a result, we chose to target only the smallest possible area for each selected algorithm. Consequently, two strategies are presented: full width and serial hardware implementations. All results were generated and verified for Xilinx Spartan‐6 and Spartan‐3 field‐programmable gate arrays and also for application‐specific integrated circuit. Additionally, all the design files are available online. Copyright © 2016 John Wiley & Sons, Ltd.
This article describes lightweight hardware implementations of four recent block ciphers (Klein, Led, Lilliput, and Ktantan). In this work, we chose to target only the smallest possible area for each selected algorithm. The results given in this article were generated and checked (using post place and route simulations) for Xilinx Spartan 6 FPGAs and for Xilinx Spartan 3. Additionally, all the design files are available online.