Generating a checking sequence with a minimum number of reset transitions
Given a finite state machine M , a checking sequence is an input sequence that is guaranteed to lead to a failure if the implementation under test is faulty and has no more states than M . There has been much interest in the automated generation of a short checking sequence from a finite state machi...
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| Published in: | Automated software engineering Vol. 17; no. 3; pp. 217 - 250 |
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| Language: | English |
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01-09-2010
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| Abstract | Given a finite state machine
M
, a checking sequence is an input sequence that is guaranteed to lead to a failure if the implementation under test is faulty and has no more states than
M
. There has been much interest in the automated generation of a short checking sequence from a finite state machine. However, such sequences can contain reset transitions whose use can adversely affect both the cost of applying the checking sequence and the effectiveness of the checking sequence. Thus, we sometimes want a checking sequence with a minimum number of reset transitions rather than a shortest checking sequence. This paper describes a new algorithm for generating a checking sequence, based on a distinguishing sequence, that minimises the number of reset transitions used. |
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| AbstractList | Given a finite state machine M, a checking sequence is an input sequence that is guaranteed to lead to a failure if the implementation under test is faulty and has no more states than M. There has been much interest in the automated generation of a short checking sequence from a finite state machine. However, such sequences can contain reset transitions whose use can adversely affect both the cost of applying the checking sequence and the effectiveness of the checking sequence. Thus, we sometimes want a checking sequence with a minimum number of reset transitions rather than a shortest checking sequence. This paper describes a new algorithm for generating a checking sequence, based on a distinguishing sequence, that minimises the number of reset transitions used. Given a finite state machine M , a checking sequence is an input sequence that is guaranteed to lead to a failure if the implementation under test is faulty and has no more states than M . There has been much interest in the automated generation of a short checking sequence from a finite state machine. However, such sequences can contain reset transitions whose use can adversely affect both the cost of applying the checking sequence and the effectiveness of the checking sequence. Thus, we sometimes want a checking sequence with a minimum number of reset transitions rather than a shortest checking sequence. This paper describes a new algorithm for generating a checking sequence, based on a distinguishing sequence, that minimises the number of reset transitions used. |
| Author | Ural, H. Hierons, R. M. |
| Author_xml | – sequence: 1 givenname: R. M. surname: Hierons fullname: Hierons, R. M. email: rob.hierons@brunel.ac.uk organization: Department of Information Systems and Computing, Brunel University – sequence: 2 givenname: H. surname: Ural fullname: Ural, H. organization: School of Information Technology and Engineering, University of Ottawa |
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| Cites_doi | 10.1109/5.533956 10.1002/net.3230060305 10.1109/32.265636 10.1007/978-3-540-75101-4_30 10.1147/sj.411.0089 10.1109/32.87284 10.1109/TSE.1978.231496 10.1109/TC.2004.1275300 10.1016/j.ipl.2004.03.003 10.1109/T-C.1970.222975 10.1109/12.559807 10.1109/TC.2006.80 10.1109/TC.2002.1032630 10.1016/B978-0-12-417750-5.50022-1 10.1109/JPROC.1996.533955 10.1007/BFb0024651 10.1109/SWCT.1964.8 10.1007/978-3-540-30232-2_8 |
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| Keywords | Distinguishing sequence Reset transition Checking sequence generation Optimisation Finite state machine |
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| References | Ural, Wu, Zhang (CR25) 1997; 46 Fujiwara, Bochmann, Khendek, Amalou, Ghedamsi (CR11) 1991; 17 Farchi, Hartman, Pinter (CR9) 2002; 41 Hierons (CR16) 2004; 90 CR15 Moore, Shannon, McCarthy (CR24) 1956 da Silva Simão, Petrenko (CR6) 2008 Aho, Dahbura, Lee, Uyar (CR1) 1988 Gonenc (CR12) 1970; 19 Harel, Politi (CR13) 1998 Chow (CR5) 1978; 4 Hopcroft, Kohavi (CR19) 1971 Luo, Bochmann, Petrenko (CR23) 1994; 20 Yao, Petrenko, Bochmann (CR27) 1993 Vasilevskii (CR26) 1973 Friske, Schlingloff (CR10) 2007 Dick, Faivre (CR7) 1993 Hierons, Ural (CR18) 2006; 55 Haydar, Petrenko, Sahraoui (CR14) 2004 Lee, Yannakakis (CR21) 1996; 84 Binder (CR3) 1999 Broekman, Notenboom (CR4) 2003 CR20 Lenstra, Khan (CR22) 1976; 6 Barnett, Grieskamp, Nachmanson, Schulte, Tillmann, Veanes (CR2) 2003 Duale, Uyar (CR8) 2004; 53 Hierons, Ural (CR17) 2002; 51 J.E. Hopcroft (61_CR19) 1971 R.M. Hierons (61_CR17) 2002; 51 R.M. Hierons (61_CR18) 2006; 55 T.S. Chow (61_CR5) 1978; 4 M. Friske (61_CR10) 2007 M.P. Vasilevskii (61_CR26) 1973 M. Yao (61_CR27) 1993 H. Ural (61_CR25) 1997; 46 A. Silva Simão da (61_CR6) 2008 R.V. Binder (61_CR3) 1999 B. Broekman (61_CR4) 2003 61_CR15 G. Gonenc (61_CR12) 1970; 19 J.L. Lenstra (61_CR22) 1976; 6 M. Haydar (61_CR14) 2004 E. Farchi (61_CR9) 2002; 41 J. Dick (61_CR7) 1993 A.Y. Duale (61_CR8) 2004; 53 D. Lee (61_CR21) 1996; 84 D. Harel (61_CR13) 1998 G.L. Luo (61_CR23) 1994; 20 S. Fujiwara (61_CR11) 1991; 17 61_CR20 R.M. Hierons (61_CR16) 2004; 90 E.P. Moore (61_CR24) 1956 M. Barnett (61_CR2) 2003 A.V. Aho (61_CR1) 1988 |
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Hopcroft – volume: 19 start-page: 551 year: 1970 ident: 61_CR12 publication-title: IEEE Trans. Comput. doi: 10.1109/T-C.1970.222975 contributor: fullname: G. Gonenc – volume: 84 start-page: 1089 issue: 8 year: 1996 ident: 61_CR21 publication-title: Proc. IEEE doi: 10.1109/JPROC.1996.533955 contributor: fullname: D. Lee – start-page: 301 volume-title: 26th International Conference on Computer Safety, Reliability, and Security (SAFECOMP) year: 2007 ident: 61_CR10 doi: 10.1007/978-3-540-75101-4_30 contributor: fullname: M. Friske – volume-title: Automata Studies year: 1956 ident: 61_CR24 contributor: fullname: E.P. Moore – volume: 51 start-page: 1111 issue: 9 year: 2002 ident: 61_CR17 publication-title: IEEE Trans. Comput. doi: 10.1109/TC.2002.1032630 contributor: fullname: R.M. Hierons – volume-title: Modeling Reactive Systems with Statecharts: The STATEMATE Approach year: 1998 ident: 61_CR13 contributor: fullname: D. Harel – volume: 17 start-page: 591 issue: 6 year: 1991 ident: 61_CR11 publication-title: IEEE Trans. Softw. Eng. doi: 10.1109/32.87284 contributor: fullname: S. Fujiwara – volume: 53 start-page: 614 issue: 5 year: 2004 ident: 61_CR8 publication-title: IEEE Trans. Comput. doi: 10.1109/TC.2004.1275300 contributor: fullname: A.Y. Duale – volume: 46 start-page: 93 issue: 1 year: 1997 ident: 61_CR25 publication-title: IEEE Trans. Comput. doi: 10.1109/12.559807 contributor: fullname: H. Ural – volume-title: Failure Diagnosis of Automata. Cybernetics year: 1973 ident: 61_CR26 contributor: fullname: M.P. Vasilevskii – volume: 4 start-page: 178 year: 1978 ident: 61_CR5 publication-title: IEEE Trans. Softw. Eng. doi: 10.1109/TSE.1978.231496 contributor: fullname: T.S. Chow – start-page: 268 volume-title: FME ’93, First International Symposium on Formal Methods in Europe year: 1993 ident: 61_CR7 doi: 10.1007/BFb0024651 contributor: fullname: J. Dick – volume: 41 start-page: 89 issue: 1 year: 2002 ident: 61_CR9 publication-title: IBM Syst. J. doi: 10.1147/sj.411.0089 contributor: fullname: E. Farchi – ident: 61_CR15 doi: 10.1109/SWCT.1964.8 – start-page: 75 volume-title: Protocol Specification, Testing, and Verification VIII year: 1988 ident: 61_CR1 contributor: fullname: A.V. Aho – start-page: 115 volume-title: Formal Techniques for Networked and Distributed Systems (FORTE 2004) year: 2004 ident: 61_CR14 doi: 10.1007/978-3-540-30232-2_8 contributor: fullname: M. Haydar – start-page: 252 volume-title: Formal Approaches to Testing year: 2003 ident: 61_CR2 contributor: fullname: M. Barnett – volume: 6 start-page: 273 year: 1976 ident: 61_CR22 publication-title: Networks doi: 10.1002/net.3230060305 contributor: fullname: J.L. Lenstra – ident: 61_CR20 – volume-title: Testing Object-Oriented Systems: Models, Patterns, and Tools year: 1999 ident: 61_CR3 contributor: fullname: R.V. Binder – start-page: 241 volume-title: Protocol Specification, Testing and Verification, XIII (C-16) year: 1993 ident: 61_CR27 contributor: fullname: M. Yao – volume-title: Testing Embedded Software year: 2003 ident: 61_CR4 contributor: fullname: B. Broekman – start-page: 153 volume-title: 20th IFIP TC 6/WG 6.1 International Conference Testing of Software and Communicating Systems, 8th International Workshop on Formal Approaches to Testing of Software (TestCom/FATES 2008) year: 2008 ident: 61_CR6 contributor: fullname: A. Silva Simão da |
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| Snippet | Given a finite state machine
M
, a checking sequence is an input sequence that is guaranteed to lead to a failure if the implementation under test is faulty... Given a finite state machine M, a checking sequence is an input sequence that is guaranteed to lead to a failure if the implementation under test is faulty and... |
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| SubjectTerms | Algorithms Artificial Intelligence Computer Science Finite state machines Software Engineering/Programming and Operating Systems |
| Title | Generating a checking sequence with a minimum number of reset transitions |
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