The relentless march of the MOSFET gate oxide thickness to zero

The relentless march of the MOSFET gate oxide thickness to zero

The narrowest feature of an integrated circuit is the silicon dioxide gate dielectric (3–5 nm). The viability of future CMOS technology is contingent upon thinning the oxide further to improve drive performance, while maintaining reliability. Practical limitations due to direct tunneling through the...

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Bibliographic Details
Published in:Microelectronics and reliability Vol. 40; no. 4-5; pp. 557 - 562
Main Authors: Timp, G, Bude, J, Baumann, F, Bourdelle, K.K, Boone, T, Garno, J, Ghetti, A, Green, M, Gossmann, H, Kim, Y, Kleiman, R, Kornblit, A, Klemens, F, Moccio, S, Muller, D, Rosamilia, J, Silverman, P, Sorsch, T, Timp, W, Tennant, D, Tung, R, Weir, B
Format: Journal Article
Language:English
Published: Elsevier Ltd 01-04-2000
Online Access:Get full text
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Summary:The narrowest feature of an integrated circuit is the silicon dioxide gate dielectric (3–5 nm). The viability of future CMOS technology is contingent upon thinning the oxide further to improve drive performance, while maintaining reliability. Practical limitations due to direct tunneling through the gate oxide may preclude the use of silicon dioxide as the gate dielectric for thicknesses less than 1.3 nm, however.
ISSN:0026-2714
1872-941X
DOI:10.1016/S0026-2714(99)00257-7