Numerical analysis of thermo-mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits

• Published in: Microelectronic engineering Vol. 87; no. 2; pp. 208 - 215
• Main Author: Ladani, Leila J.
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01-02-2010; Elsevier
• Subjects: 3D ICs; Applied sciences; Brazing. Soldering; Design. Technologies. Operation analysis. Testing; Durability; Electronics; Exact sciences and technology; Finite element; Fractures; Integrated circuits; Joining, thermal cutting: metallurgical aspects; Mechanical properties and methods of testing. Rheology. Fracture mechanics. Tribology; Metals. Metallurgy; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Through silicon vias; Durability; Through silicon vias; 3D ICs; Finite element; Interfacial layer; Thermal cycle; Numerical method; Continuum; Solder; Integrated circuit bonding; Hardening; Three dimensional structure; Electronic packaging; Silicon; Copper; Three level system; Fatigue life; Die; Active layer; Thermal load; Thickness; Three dimensional model; Interconnection; Soldered joint; Integrated circuit; Numerical simulation; Miniaturization; Reliability; Plastics; Via hole
• ISSN: 0167-9317; 1873-5568
• DOI: 10.1016/j.mee.2009.07.022

Three-dimensional integrated circuit (3D IC) is a promising technology in today’s IC packaging industry. Since the technology is in infancy stages, many aspects of this technology are still under heavy investigation. Reliability of through silicon via (TSV) interconnects and interlayer bondings between the silicon layers are issues that become more complicated in 3D ICs due to the complexity of the architecture and miniaturized interconnect. Optimizing design of these devices is essential in order to avoid short fatigue life of interconnects. This manuscript addresses the impact of design parameters such as die thickness, TSV diameter and pitch, and underfill thickness and properties on thermo-mechanical durability of direct chip attach (DCA) solder joints and TSV interconnects used in a 3D IC packages. A design was proposed where DCA is used to connect four layers of ICs and TSVs are used to connect the active layer of the dies to the second silicon layer. Solder joints, as small as 50
μm diameter, were used to attach silicon layers. A numerical experiment is designed to vary these factors at three levels using L9 orthogonal array. A 3-dimensional model of the package was built and model was solved under an accelerated thermal cycle loading. Solder is considered to be visco-plastic material and copper interconnects are assumed to follow bi-linear isotropic hardening behavior. Two continuum damage models; energy-partitioning (E-P) and Coffin–Manson; were used to assess the number of cycles to failure for solder joints and TSV copper interconnects, respectively. Minitab software was used to analyze the result of experiment and general linear model analysis of variance (GLMANOVA) was used to evaluate significance of each factor. The most influential factors on durability of solder interconnect are found to be underfill properties and height. However, the most influential factor on TSV durability is found to be TSV diameter. A non-linear response was observed for TSV pitch and diameter indicating that the optimum level is in the range selected. Location of failures was also found to depend on selected parameters and be a function of effective CTE. A simple analytical approach is presented to estimate the effective CTE for silicon layers containing TSVs. Effective CTE can be varied as one of the design parameters to achieve optimum design.