Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 56; no. 1; pp. 56 - 60
• Main Authors: Song, Jaehoon, Han, Juhee, Yi, Hyunbean, Jung, Taejin, Park, Sungju
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-01-2009; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Circuit faults; Circuit testing; Circuits; Circuits and systems; Crosstalk; Crosstalk faults; Delay; Errors; Faults; Integrated circuit interconnections; interconnect test; static faults; System on chip; System testing; System-on-a-chip; system-on-a-chip (SoC); test pattern; Test pattern generators; Timing
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2008.2010168

The effect of crosstalk-induced errors becomes more significant in high-performance circuits and systems. In this paper, compact crosstalk test patterns are introduced for a system-on-a-chip and board level interconnects considering physically effective aggressors. By being able to target multiple victim lines, 6 n , where n is the number of nets patterns are drastically reduced to a constant number 6 D , where D indicates the effective distance among interconnect nets. The test quality for static and crosstalk faults are completely preserved with 6 D patterns.