Impact of Technology Scaling and Back-end-of-the-line Technology Solutions on Magnetic Random-Access Memories

• Published in: IEEE journal on exploratory solid-state computational devices and circuits Vol. 10; p. 1
• Main Authors: Kumar, Piyush, Shim, Da Eun, Narla, Siri, Naeemi, Azad
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01-01-2024; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arrays; Back-end-of-the-line; Back-end-of-the-line (BEOL); CAD; Computer aided design; Frequency modulation; Integrated circuit interconnections; interconnect; magnetic random access memory; magnetic random-access memory (MRAM); Magnetic tunneling; Nodes; Performance evaluation; Random access memory; Resistance; spin-orbit torque; spin-orbit torque (SOT); spin-transfer torque; spin-transfer torque (STT); Switches; Torque; Wires
• DOI: 10.1109/JXCDC.2024.3357625
• EISSN: 2329-9231

While magnetic random-access memories (MRAMs) are promising thanks to their non-volatility, relatively fast speeds, and high endurance, there are major challenges in adopting them for the advanced technology nodes. One of the major challenges in scaling MRAM devices is caused by the ever increasing resistances of interconnects. In this paper, we first study the impact of shrunk interconnect dimensions on MRAM performance at various technology nodes. Then, we investigate the impact of various potential back-end-of-the-line (BEOL) technology solutions at the 7nm node. Based on interconnect resistance values from TCAD simulations and MRAM device characteristics from experimentally validated/calibrated physical models, we quantify the potential array-level performance of MRAM using SPICE simulations. We project that some potential BEOL technology solutions can reduce the write energy by up to 34.6% with spin-orbit torque (SOT) MRAM, and 29.0% with spin-transfer torque (STT) MRAM. We also observe up to 21.4% reduction in the read energy of the SOT-MRAM arrays.