Design and Optimization of Triple-k Spacer Structure in Two-Stack Nanosheet FET From OFF-State Leakage Perspective

• Published in: IEEE transactions on electron devices Vol. 67; no. 3; pp. 1317 - 1322
• Main Authors: Ryu, Donghyun, Kim, Munhyeon, Kim, Sihyun, Choi, Yunho, Yu, Junsu, Lee, Jong-Ho, Park, Byung-Gook
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-03-2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Atomic layer epitaxy; Design optimization; Dispersion; Field effect transistors; Gallium arsenide; Gate-induced drain leakage (GIDL); inner spacer; leakage current; Logic gates; Nanosheets; Optimization; Performance evaluation; Permittivity; spacer material; stack nanosheet FET (NSFET); structure optimization; triple-k spacer
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2020.2969445

In this article, a 5-nm node two-stack nanosheet FET with a triple-k spacer structure representing three spacer regions consisting of two inner spacers (inner spacer 1 and inner spacer 2) formed by two atomic layer deposition (ALD) processes leveraging the inner spacer formation-process method and outer spacer process of stack gate-all-around (GAA) process is proposed. Material and structure optimization was performed to confirm the effects of each spacer regions. Inner spacer 1 has a direct effect on the channel extension region. However, the inner spacer 2 is not in direct contact with the channel extension region and the gate, thus confirming the relatively indirect effect. In addition, the material dependence of the outer spacer, formed between the gate and the side region of the channel where the field is concentrated, was confirmed. By comparing the optimized triple-k spacer structure with the fully nitride spacer, the improved dynamic performance, as well as the active power and static power, was identified.