Experimental Demonstration of Gate-Level Logic Camouflaging and Run-Time Reconfigurability Using Ferroelectric FET for Hardware Security

• Published in: IEEE transactions on electron devices Vol. 68; no. 2; pp. 516 - 522
• Main Authors: Dutta, Sourav, Grisafe, Benjamin, Frentzel, Chloe, Enciso, Zephan, Jose, Matthew San, Smith, Jeffrey, Ni, Kai, Joshi, Siddharth, Datta, Suman
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-02-2021; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Boolean algebra; Camouflage; Camouflage logic; Carrier injection; FeFETs; ferroelectric; ferroelectric field-effect transistor (FeFET); Ferroelectric materials; Ferroelectricity; Field effect transistors; Hardware; hardware security; Integrated circuits; Intellectual property; Layout; Logic; Logic gates; Reverse engineering; Security; Semiconductor devices; Theft; Threshold voltage; Topology; Transistors; Voltage measurement
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2020.3045380

Outsourcing of integrated circuit (IC) manufacturing and increasing sophistication of IC reverse engineering techniques have unleashed security threats such as intellectual property (IP) theft and insertion of hardware Trojans. In this article, we propose and implement a run-time reconfigurable camouflage logic technology based on ferroelectric field-effect transistor (FeFET). The technology simultaneously obfuscates design IP from zero-trust foundry and untrusted testing facility and thwarts reverse engineering and counterfeiting threat. We fabricate for the first time an eight FeFET-based circuit block and demonstrate in silico gate-level camouflaging by implementing three Boolean logic functions-NOR, NAND, and XNOR-in the same circuit topology using threshold voltage (<inline-formula> <tex-math notation="LaTeX">{V}_{\text {T}} </tex-math></inline-formula>) programming of FeFET. We perform circuit simulations using empirically calibrated models to estimate power, latency, and area overhead. Compared with recent proposal of programmable camouflage logic using hot-carrier injection (HCI), FeFET offers an overhead reduction of <inline-formula> <tex-math notation="LaTeX">2\times </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">1.8\times </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">2.8\times </tex-math></inline-formula> in area, power, and delay, respectively.