A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 16; no. 8; pp. 975 - 984
• Main Authors: Mahalingam, V., Ranganathan, N., Harlow, J.E.
• Format: Journal Article
• Language: English
• Published: Piscataway, NJ IEEE 01-08-2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Benchmark testing; Circuit optimization; Circuit testing; Delay; Design automation; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Fuzzy logic; fuzzy optimization; gate sizing; Integrated circuit technology; Integrated circuit yield; Integrated circuits; Linear programming; Minimization; process variations; Robustness; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Studies; Transistors; Uncertainty; Monte Carlo method; Averaging method; Membership function; Design automation; gate sizing; Resistive circuit; fuzzy optimization; Linear programming; Transistor; Nonlinear problems; Algorithm; Optimization; Dimensioning; process variations; Integrated circuit; Numerical simulation; Fan out; Robustness; Delay time; Deterministic approach; Execution time
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2008.2000597

Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact on the yield of the integrated circuits and need to be considered early in the design flow. Traditional corner based deterministic methods are no longer effective and circuit optimization methods require reinvention with a statistical perspective. In this paper, we propose a new gate sizing algorithm using fuzzy linear programming in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay which is a function of the gate sizes and the fan-outs of the gates are represented using triangular fuzzy numbers with linear membership functions. Initially, as a preprocessing step for fuzzy optimization, we perform deterministic optimizations by fixing the fuzzy parameters to the worst and the average case values, the results of which are used to convert the fuzzy optimization problem into a crisp nonlinear problem. The crisp problem with delay and power as constraints is then formulated to maximize the robustness, i.e., the variation resistance of the circuit. The fuzzy optimization approach was tested on ITC'99 benchmark circuits and the results were validated for timing yield using Monte Carlo simulations. The proposed approach is shown to achieve better power reduction than the worst case deterministic optimization as well as the stochastic programming based gate sizing methods, while having comparable runtimes.