An FPGA Implementation of MML-DFE for Spatially Multiplexed MIMO Systems

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 55; no. 7; pp. 705 - 709
• Main Authors: Yu, Sungwook, Im, Tae Ho, Park, Chang Hwan, Kim, Jaekwon, Cho, Yong Soo
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-07-2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Blocking; Circuits; Complexity; Computation; Computational complexity; Decision feedback equalizers; Decision-feedback equalization (DFE); Degradation; Equalization; Field programmable gate arrays; Frequency-selective fading channels; Hardware; Maximum likelihood detection; maximum-likelihood (ML) detection; MIMO; multi-input multi-output (MIMO); Multiplexing; Receiving antennas; Signal detection
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2008.921572

Although the maximum-likelihood decision-feedback equalization (ML-DFE) detection method for multi-input multi- output (MIMO) system leads to a good compromise between the performance and the complexity, the computational complexity of the ML part in the ML-DFE is still large. This paper describes a modified maximum-likelihood (MML) algorithm, which reduces the computational complexity of the original ML algorithm significantly without degrading the performance. Then, based on the MML algorithm, we propose the MML-DFE, which has the same performance as the ML-DFE but has much lower complexity. Both the ML-DFE block and MML-DFE block for 4times4 MIMO system have been implemented in field-programmable gate array to verify the functional correctness and the complexity advantage.