Low-cost microoptical modules for MCM level optical interconnections

• Published in: IEEE journal of selected topics in quantum electronics Vol. 9; no. 2; pp. 518 - 530
• Main Authors: Debaes, C., Vervaeke, M., Baukens, V., Ottevaere, H., Vynck, P., Tuteleers, P., Volckaerts, B., Meeus, W., Brunfaut, M., Van Campenhout, J., Hermanne, A., Thienpont, H.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-03-2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Aggregates; Bit rate; Circuit testing; Logic arrays; Optical arrays; Optical design; Optical interconnections; Optical receivers; Optical refraction; Programmable logic arrays; Semiconductors
• ISSN: 1077-260X; 1558-4542
• DOI: 10.1109/JSTQE.2003.813316

A multichannel free-space microoptical module for dense MCM-level optical interconnections has been designed and fabricated. Extensive modeling proves that the module is scalable with a potential for multi-Tb/s/spl middot/cm/sup 2/ aggregate bit rate capacity while alignment and fabrication tolerances are compatible with present-day mass replication techniques. The microoptical module is an assembly of refractive lenslet-arrays and a high-quality microprism. Both components are prototyped using deep lithography with protons and are monolithically integrated using a vacuum casting replication technique. The resulting 16-channel high optical-grade plastic module shows optical transfer efficiencies of 46% and inter-channel cross talks as low as -22 dB, sufficient to establish workable multichannel MCM-level interconnections. This microoptical module was used in a feasibility demonstrator to establish intra-chip optical interconnections on a 0.6 /spl mu/m CMOS optoelectronic field programmable gate array. This optoelectronic chip combines fully functional digital logic, driver and receiver circuitry and flip-chipped VCSEL and detector arrays. With this test-vehicle multichannel on-chip data-communication has been achieved for the first time to our knowledge. The bit rate per channel was limited to 10 Mb/s because of the limited speed of the chip tester.