Level C+ data reuse scheme for motion estimation with corresponding coding orders

• Published in: IEEE transactions on circuits and systems for video technology Vol. 16; no. 4; pp. 553 - 558
• Main Authors: CHEN, Ching-Yeh, HUANG, Chao-Tsung, CHEN, Yi-Hau, CHEN, Liang-Gee
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-04-2006; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Bandwidth; Chaotic communication; Circuits; Coding; Coding, codes; Concurrent computing; Data reuse; Energy consumption; Exact sciences and technology; Hardware; HDTV; Information, signal and communications theory; memory bandwidth; Microprocessors; Miscellaneous; Motion estimation; MPEG 4 Standard; Power consumption; Reuse; Searching; Semiconductors; Signal and communications theory; Signal processing; Specifications; Telecommunications and information theory; Video coding; Video compression; Video coding; memory bandwidth; Data reuse; Motion estimation; Video signal processing; Reuse
• ISSN: 1051-8215; 1558-2205
• DOI: 10.1109/TCSVT.2006.871388

The memory bandwidth reduction for motion estimation is important because of the power consumption and limited memory bandwidth in video coding systems. In this paper, we propose a Level C+ scheme which can fully reuse the overlapped searching region in the horizontal direction and partially reuse the overlapped searching region in the vertical direction to save more memory bandwidth compared to the Level C scheme. However, direct implementation of the Level C+ scheme may conflict with some important coding tools and then induces a lower hardware efficiency of video coding systems. Therefore, we propose n-stitched zigzag scan for the Level C+ scheme and discuss two types of 2-stitched zigzag scan for MPEG-4 and H.264 as examples. They can reduce memory bandwidth and solve the conflictions. When the specification is HDTV 720p, where the searching range is [-128,128), the required memory bandwidth is only 54%, and the increase of on-chip memory size is only 12% compared to those of traditional Level C data reuse scheme.