Power distribution techniques for VLSI circuits

• Published in: IEEE journal of solid-state circuits Vol. 21; no. 1; pp. 150 - 156
• Main Authors: Song, W.S., Glasser, L.A.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-02-1986; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Current density; Electronics; Exact sciences and technology; Integrated circuit interconnections; Integrated circuits; Nonhomogeneous media; Optical interconnections; Power distribution; Routing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Space technology; Very large scale integration; Voltage; Wire; Power supply; VLSI circuit; Integrated circuit
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.1986.1052491

The onchip power distribution problem for highly scaled technologies is investigated. Metal migration and line resistance problems as well as ways to optimize multilayer metal technology for low resistance, low current density, and maximum wirability are also investigated. Fundamental lower limits and the limiting factors of the power-line current density and the voltage drop are studied. Tradeoffs between interconnect wirability and power distribution space are examined. Power routing schemes, as well as the optical number of metal layers and the optimal thickness of each layer, are examined. The results indicate that orders of magnitude improvements in current density and resistive voltage drop can be achieved using very few layers of thick metal whose thicknesses increase rapidly in ascending layers. Also, using the upper layers for power distribution and lower layers for signal routing results in the most wire length available for signal routing.