Comparison of Dual-Rail and TMR Logic Cost Effectiveness and Suitability for FPGAs With Reconfigurable SEU Tolerance

• Published in: IEEE transactions on nuclear science Vol. 56; no. 1; pp. 214 - 219
• Main Authors: Shuler, R.L., Bhuva, B.L., O'Neill, P.M., Gambles, J.W., Rezgui, S.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-02-2009; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Architecture; Circuit testing; Circuits; Complementary metal-oxide-semiconductor (CMOS); Cost effectiveness; Costs; digital circuits; field programmable gate array (FPGA); Field programmable gate arrays; Hardware; Logic; Logic circuits; Manufacturing; Modular; Protection; radiation-hardening; Reconfigurable logic; Redundancy; sequential circuits; single event; Single event upset; Strings; Tolerances
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2008.2010320

We compare four circuit methods for single event (SE) mitigation: single string with radiation-hardened flip flops, delay-guarded logic, dual-rail logic, and triple modular redundancy (TMR). Test results of the circuit methods at 180 nm are presented. We then describe a novel reprogrammable FPGA architecture which can be configured based on SE mitigation and performance needs, and we evaluate the candidate SE mitigation methods as to suitability for such architecture.