An AI-calibrated IF filter: a yield enhancement method with area and power dissipation reductions

• Published in: IEEE journal of solid-state circuits Vol. 38; no. 3; pp. 495 - 502
• Main Authors: Murakawa, M., Adachi, T., Niino, Y., Kasai, Y., Takahashi, E., Takasuka, K., Higuchi, T.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-03-2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog circuits; Artificial intelligence; Automotive engineering; Calibration; Circuit topology; Costs; Filters; Frequency; Genetic algorithms; Intermediate frequencies; Intermediate frequency; Large scale integration; Power dissipation; Reduction
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2002.808303

We have developed a large-scale integration (LSI) for Gm-C intermediate frequency (IF) filters, attaining a 63% reduction in filter area, a 26% reduction in power dissipation, compared with existing commercial products using the same process technology and filter topology, and a yield rate of 97%. The developed chip is calibrated within a few seconds by a genetic algorithm - an efficient AI technique for difficult optimization problems. Our calibration method, which can be applied to a wide variety of analog circuits, leads to cost reductions and the efficient implementation of analog LSIs.