Low-Cost Scan Test for IEEE-1500-Based SoC

• Published in: IEEE transactions on instrumentation and measurement Vol. 57; no. 5; pp. 1071 - 1078
• Main Authors: Hyunbean Yi, Hyunbean Yi, Jaehoon Song, Jaehoon Song, Sungju Park, Sungju Park
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-05-2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Automated; Automatic control; Automatic testing; Channels; Clock generators; Clocks; Control equipment; Costs; Delay; Delay test; Design for testability; design-for-testability (DfT); IEEE 1500; Instrumentation; Pins; reduced pin-count test (RPCT); System testing; System-on-a-chip; system-on-a-chip (SoC); Test equipment; reduced pin-count test (RPCT); design-for-testability (DfT); IEEE 1500; system-on-a-chip (SoC); Delay test
• ISSN: 0018-9456; 1557-9662
• DOI: 10.1109/TIM.2007.911699

In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through the IEEE-1149.1 TAP for scan delay test. By using only the IEEE- 1149.1 TAP control pins as test-access pins and by embedding an on-chip test clock generator, low-cost automated test equipment (ATE) can be efficiently utilized to reduce testing costs. Experiments show the effectiveness of our technique in utilizing the ATE channels and scan delay testing.