Teaching the Cache Memory System Using a Reconfigurable Approach

• Published in: IEEE transactions on education Vol. 51; no. 3; pp. 336 - 341
• Main Authors: Quislant, R., Herruzo, E., Plata, O., Benavides, J.I., Zapata, E.L.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-08-2008; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Architecture; Architecture (computers); Assessments; Cache memories; Computer simulation; computer-aided instruction; Education; Mathematical models; reconfigurable cache design; simulation software; Students
• ISSN: 0018-9359; 1557-9638
• DOI: 10.1109/TE.2008.916767

This paper presents a tool that simulates a reconfigurable cache whose parameters can be changed at runtime through a special instruction at the instruction set architecture (ISA) level. The proposed tool simulates a cache system that can be reconfigured within a variety of 298 combinations of cache capacity, number of ways or associativity, and line/block size in words (C, W, and L) without changing its architecture. The simulator was developed through a series of laboratory exercises in computer architecture. The students are introduced to the reconfigurable cache architecture while refreshing their knowledge on computer architecture issues like logic design, and register transfer level and computer system level architectures, as well as reinforcing concepts about memory system organization and architecture. This paper presents an overview of the reconfigurable cache and a description of the simulator interface. Finally, feedback from the students provides assessment on using the simulator in the laboratory.