Vertical isolation in shallow n-well CMOS circuits

• Published in: IEEE electron device letters Vol. 8; no. 3; pp. 107 - 109
• Main Authors: Lewis, A.G., Martin, R.A., Chen, J.Y., Tiao-Yuan Huang, Koyanagi, M.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-03-1987; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Capacitance; Circuits; CMOS technology; Degradation; Doping profiles; Electronics; Epitaxial layers; Exact sciences and technology; Integrated circuits; Protection; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Substrates; Variable structure systems; Very large scale integration; Depletion mode; VLSI circuit; Spurious capacity; Electrical insulation; Epitaxial film; Thickness; Simulation; Complementary MOS technology; Limitation; Integrated circuit; Leakage current; Junction; Triggering; Protection
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/EDL.1987.26568

This letter examines vertical punchthrough in a shallow conventional n-well suitable for use in high-packing-density VLSI CMOS circuits. It is shown that full vertical isolation can be maintained even when the well beneath a p+ diffusion is completely depleted-that is the p+-to-n-well and n-well-to-p-substrate depletion regions meet-and that this offers an advantage in terms of p+ junction capacitance. However, if thin p-on-p+ epitaxial substrate material is used for latch-up suppression, then vertical isolation can be severely degraded. This effect ultimately limits the thickness of the epitaxial layer and hence the degree of latch-up protection.