The Influence of Gate Scaling to Electrical Characteristics on n-MOS FinFET

• Published in: MATEC web of conferences Vol. 108; p. 9002
• Main Authors: Patchrasardtra, Nuttapong, Pengchan, Weera
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Les Ulis EDP Sciences 01-01-2017
• Subjects: Computer simulation; Scaling; Threshold voltage
• ISSN: 2261-236X; 2274-7214; 2261-236X
• DOI: 10.1051/matecconf/201710809002

This paper investigates effects from gate scaling in Tri-gate FinFET structure by simulation method, to avoid problems and improve a structure to be good prototype. The experiments used GTS framework for simulation. Start from 20 nm device, then scaling to 22 nm 28 nm and 32 nm. Therefrom Minimos-NT function has used for biasing to giving two electrical characteristics as the drain current saturation and the threshold voltage. From these consequences can offer the subthreshold swing and the drain-induced barrier lowering by calculation. The results found that threshold voltage inversely proportional to saturated drain current, the subthreshold swing and the drain-induced barrier lowering. The short channel effect has affected to 20 nm model by highest DIBL. Therefore should be adjust the gate length and the oxide thickness properly to improve this effect.