Through silicon in-circuit logic analysis for localizing logic pattern failures

• Published in: Microelectronics and reliability Vol. 52; no. 9-10; pp. 2043 - 2049
• Main Authors: Bruce, M.R., Ross, L.K., Scholz, C., Joshi, L., Dave, Vrajesh, Chua, C.M.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Kidlington Elsevier Ltd 01-09-2012; Elsevier
• Subjects: Applied sciences; Electric, optical and optoelectronic circuits; Electronics; Exact sciences and technology; Theoretical study. Circuits analysis and design; Case study; Silicon; Failures; Mismatching; Network analysis
• ISSN: 0026-2714; 1872-941X
• DOI: 10.1016/j.microrel.2012.06.107

Laser timing probes are used to display waveforms at single points or frequencies mapped throughout a field of view in an effort to locate logic failures. By focusing just on the logic state itself, this paper describes an approach that quickly determines the logic timing patterns and uses this information to identify logic pattern mismatches on-the-fly at specific locations, such as cells in a scan chain. Various applications and case studies are presented.