Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 66; no. 2; pp. 282 - 286
• Main Authors: Lam, Siew-Kei, Jiang, Guiyuan, Wu, Meiqing, Cao, Bin
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-02-2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Accelerated tests; Adders; Architecture; CMOS; Computation; Computer architecture; Delays; Detectors; embedded vision; Energy consumption; Feature descriptor; hardware acceleration; Registers; Smoothing methods; Streaming media; VLSI
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2018.2846683

The combination of features from an accelerated segment test (FAST) corners and binary robust independent elementary feature (BRIEF) descriptors provide highly robust image features. We present a novel detector for computing the FAST-BRIEF features from streaming images. To reduce the complexity of the BRIEF descriptor, we employ an optimized adder tree to perform summation by accumulation on streaming pixels for the smoothing operation. Since the window buffer used in existing designs for computing the BRIEF point-pairs are often poorly utilized, we propose an efficient sampling scheme that exploits register reuse to minimize the number of registers. Synthesis results based on 65-nm CMOS technology show that the proposed FAST-BRIEF core achieves over 40% reduction in area-delay product compared to the baseline design. In addition, we show that the proposed architecture can achieve 1.4× higher throughput than the baseline architecture with slightly lower energy consumption.