ESD protection for the tolerant I/O circuits using PESD implantation

• Published in: Journal of electrostatics Vol. 54; no. 3; pp. 293 - 300
• Main Authors: Tang, Howard T.H., Chen, S.S., Liu, Scott, Lee, M.T., Liu, C.H., Wang, M.C., Jeng, M.C.
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01-03-2002
• ISSN: 0304-3886; 1873-5738
• DOI: 10.1016/S0304-3886(01)00157-7

In this paper, we propose an electrostatic discharge (ESD) solution with cascode structure for deep-submicron integrated circuits technology to enhance its ESD robustness. Using the added boron implantation (we call “PESD” implantation here) at the drain side of the stacked n-type metal-oxide semiconductor (NMOS), the long-base parasitic NPN (i.e., emitter, base and collector in the bipolar transistor are n-type, p-type, and n-type, respectively) bipolar transistor in the cascode NMOS structure can be easily triggered by the Zener breakdown mechanism at the drain side under ESD stress conditions. Based on UMC 0.25
μm process, this method provides a significant improvement in the cascode ESD performance.