The vertical replacement-gate (VRG) MOSFET

• Published in: Solid-state electronics Vol. 46; no. 7; pp. 939 - 950
• Main Authors: Hergenrother, J.M., Oh, Sang-Hyun, Nigam, T., Monroe, D., Klemens, F.P., Kornblit, A.
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01-07-2002
• Subjects: Lithography-independent; MOSFET; Non-lithographic; Replacement-gate; Solid source diffusion; Vertical MOSFET; MOSFET; Replacement-gate; Lithography-independent; Solid source diffusion; Vertical MOSFET; Non-lithographic
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/S0038-1101(02)00025-4

We have fabricated and demonstrated a new device called the vertical replacement-gate (VRG) MOSFET. This is the first MOSFET ever built in which: (1) all critical transistor dimensions are controlled precisely without lithography and dry etch, (2) the gate length is defined by a deposited film thickness, independently of lithography and etch, and (3) a high-quality gate oxide is grown on a single-crystal Si channel. In addition to this unique combination, the VRG-MOSFET includes self-aligned source/drain extensions (SDEs) formed by solid source diffusion (SSD), small parasitic overlap, junction, and source/drain capacitances, and a replacement-gate approach to enable alternative gate stacks. We have demonstrated nMOSFETs with an initial VRG process, and pMOSFETs with a more mature process. Since both sides of the device pillar drive in parallel, the drive current per μm of coded width can far exceed that of advanced planar MOSFETs. Our 100 nm VRG-pMOSFETs with
t
OX=25 Å drive 615 μA/μm at 1.5 V with
I
OFF=8 nA/μm—80% more drive than specified in the 1999 ITRS Roadmap at the same
I
OFF. Our 50 nm VRG-pMOSFETs with
t
OX=25 Å approach the 1.0 V roadmap target of
I
ON=350 μA/μm at
I
OFF=20 nA/μm without the need for a hyperthin (<20 Å) gate oxide. We have described a process for integrating n-channel and p-channel VRG-MOSFETs to form side-by-side CMOS that retains the key VRG advantages while providing packing density and process complexity that is competitive with traditional planar CMOS.
All of this is achieved using current manufacturing methods,
materials,
and tools, and high-performance devices with 50 nm physical gate lengths (
L
G) have been demonstrated with precise gate length control without advanced lithography.