A 3-D Circuit Model to evaluate CDM performance of ICs

This paper presents a physical description of the static charge flow through an IC during a CDM event. Based on this description, an equivalent 3-D circuit to model the complete IC under CDM stress is proposed. The model takes into account various factors like package parasitics, substrate resistanc...

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Bibliographic Details
Published in:	Microelectronics and reliability Vol. 45; no. 9; pp. 1425 - 1429
Main Authors:	Sowariraj, M.S.B., Smedes, Theo, de Jong, Peter C., Salm, Cora, Mouthaan, Ton, Kuper, Fred G
Format:	Journal Article Conference Proceeding
Language:	English
Published:	Oxford Elsevier Ltd 01-09-2005 Elsevier
Subjects:	Applied sciences Design. Technologies. Operation analysis. Testing Electronic equipment and fabrication. Passive components, printed wiring boards, connectics Electronics Exact sciences and technology Integrated circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Transistors Performance evaluation Transistor gate Contact resistance Bus(channel) Failures Three dimensional model Interconnection Gate oxide Power system protection Electronic packaging Integrated circuit Equivalent circuit Parasitic resistance Robustness MOS transistor
Online Access:	Get full text
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