An Energy-Efficient NoC Router with Adaptive Fault-Tolerance Using Channel Slicing and On-Demand TMR

• Published in: IEEE transactions on emerging topics in computing Vol. 6; no. 4; pp. 538 - 550
• Main Authors: Cheng Li, Mo Yang, Ampadu, Paul
• Format: Journal Article
• Language: English
• Published: New York IEEE 01-10-2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: channel slicing; Circuit faults; Energy; Energy efficiency; energy efficient; Fault diagnosis; Fault tolerance; Fault tolerant systems; Logic gates; Maintenance engineering; multiple physical networks; Nanotechnology; NoC router; Ports (Computers); Power efficiency; power gating; Slicing; TMR; Tunneling magnetoresistance; Very large scale integration
• ISSN: 2168-6750; 2168-6750
• DOI: 10.1109/TETC.2016.2597799

The competing goals of energy-efficiency, performance, and fault tolerance have not been well bridged in current NoC designs. In this paper, we propose an energy-efficient NoC router that exhibits strong fault-tolerance by leveraging channel slicing. This router has three identical router slices connected with internal sharing paths. Channel slicing reduces the overhead of applying power gating to improve energy-efficiency. When faults occur in any of the slices, resource sharing is enabled to enhance fault-tolerance. These router slices can also be harnessed for on-demand TMR, to further improve fault-tolerance and reduce the need for deploying costly on-chip testers. Our method can diagnose and repair both control and datapath faults without interrupting normal NoC operations. Experimental results show that our proposed router can tolerate 180 percent more gate faults than the state-of-the-art fault-tolerant NoC router architecture HPR. In addition, 64 percent energy improvement at low injection rate, and 28 percent energy improvement at high injection rate are achieved compared to HPR. Furthermore, our method attains 100 percent higher throughput (with 40 faults in one router) compared to HPR. Our proposed method increases router logic area by 7.8 percent compared to baseline.