BiCMOS circuit technology for high-speed DRAMs

• Published in: IEEE journal of solid-state circuits Vol. 28; no. 1; pp. 4 - 9
• Main Authors: Watanabe, S., Sakui, K., Fuse, T., Hara, T., Aritome, S., Hieda, K.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01-01-1993; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; BiCMOS integrated circuits; Circuit testing; Clocks; CMOS technology; Differential amplifiers; Electronics; Exact sciences and technology; Flip-flops; Impedance; Integrated circuits; Integrated circuits by function (including memories and processors); Inverters; Mirrors; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Random access memory(RAM); Circuit design; Complementary MOS technology; Dynamical storage; Bipolar technology; Amplifier; Performance; Block diagram
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.179197

A BiCMOS circuit technology featured by a novel bit-line sense amplifier has been developed. The bit-line sense amplifier is composed of a BiCMOS differential amplifier, the impedance-converting means featured by the CMOS current mirror circuit or the clocked CMOS inverter between the bit line and the base node of the BiCMOS differential amplifier, and a conventional CMOS flip-flop. This technology can reduce the access time to half that of a conventional CMOS DRAM access time. Applied to a 1-kb DRAM test chip, a new BiCMOS circuit technology was successfully verified. Furthermore, the sensitivity and area penalty of the new BiCMOS bit-line sense amplifier and future applications to megabit DRAMs are discussed.< >