The Influence of Repetitive UIS on Electrical Properties of Advanced Automotive Power Transistors

• Published in: Advances in electrical and electronic engineering Vol. 20; no. 1; pp. 86 - 94
• Main Authors: Marek, Juraj, Kozarik, Jozef, Minarik, Michal, Chvala, Ales, Stuchlikova, Lubica
• Format: Journal Article
• Language: English
• Published: Ostrava Faculty of Electrical Engineering and Computer Science VSB - Technical University of Ostrava 01-03-2022; VSB-Technical University of Ostrava
• Subjects: Avalanches; CAD; Capacitance; Carrier injection; Computer aided design; Defects; Degradation; dlts; Electrical properties; Electronic devices; Energy levels; Impact analysis; MOSFETs; P-n junctions; Parameters; Power semiconductor devices; repetitive avalanching; repetitive unclamped inductive switching (uis); Space charge; Switching; tcad; Threshold voltage; Transistors
• ISSN: 1336-1376; 1804-3119
• DOI: 10.15598/aeee.v20i1.4120

This paper investigates a degradation of three types of automotive power MOSFETs through repetitive Unclamped Inductive Switching (UIS) test typically used to evaluate the avalanche robustness of power devices. It is not uncommon in switching applications that greater than the planned voltage for voltage spikes can occur, so even the best electronic designs may encounter frequent avalanche events. Hence, there is a need to analyse the impact of repetitive avalanching on the electrical performance of power transistors. This article focused on the shift of main electrical parameters: on-resistance R_{ON}, breakdown voltage V_{BR}, threshold voltage V_{TH}, and corresponding characteristics, as well as capacitances. Analysis proved that DMOS transistors are less vulnerable to repetitive avalanching. The most impacted parameter was on-resistance R_{DSon}, where a 14 % increase was observed after 6 x 10^7 stress pulses. The parameters shift is attributed to hot carrier injection in the space charge region of blocking PN junction and involves mainly defects generation/activation in the drain side region of the gate oxide. For the TrenchMOS transistor, a significant shift of I-V curves was observed with considerable impact on the R_{ON} where an increase of 22 % was observed. The trench corner is verified to be the mainly degraded region by Synopsys Technology Computer Aided Design (TCAD) simulations. Degradation of drain-gate capacitance C_{DG} and input capacitance C_{in} was observed in all three types of analysed structures. DLTS was used to verify the generation/activation of defects invoked by stress. An increase of DLTS signal corresponding to energy levels of oxygen vacancies and impurities in SiO_2 and on interfaces were detected on stressed samples.