A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices

• Published in: IEEE MICRO Vol. 39; no. 1; pp. 24 - 32
• Main Authors: Xie, Mimi, Pan, Chen, Zhang, Youtao, Hu, Jingtong, Liu, Yongpan, Xue, Chun Jason
• Format: Journal Article
• Language: English
• Published: Los Alamitos IEEE 01-01-2019; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Arrays; Checkpointing; Computer memory; Embedded systems; Energy consumption; Energy harvesting; Internet of Things; Nonvolatile memory; Program processors; Random access memory; Registers; Restoration; Static random access memory
• ISSN: 0272-1732; 1937-4143
• DOI: 10.1109/MM.2018.2890257

Emerging nonmemory technologies have been widely employed in intermittently powered the Internet of Things (IoT) devices to bridge program execution across different power cycles. Together with register contents, the cache contents will be checkpointed to nonvolatile memory upon power outages. While pure nonvolatile memory-based cache is an intuitive option, it suffers from inferior performance due to high write latency and energy overhead. We introduce a spin-transfer torque magnetic random-access memory (STT-RAM)-based hybrid cache which is specifically tailored for the intermittently powered embedded system. This cache design supports both normal memory access and checkpointing: During normal access, the large density of STT-RAM and the fast access speed of static random-access memory (SRAM) are fully taken advantage to achieve high performance and low energy consumption; during checkpointing, the most important cache blocks in SRAM are migrated to the dead or unimportant clean cache blocks in STT-RAM. This design achieves instant resumption speed without restoration of large cache state. The experimental results demonstrate a 1.3× execution progress improvement compared with a pure nonvolatile cache design.