Recursive bi-partitioning of netlists for large number of partitions
In many application in VLSI CAD, a given netlist has to be partitioned into smaller sub-designs which can be handled much better. In this paper we present a new recursive bi-partitioning algorithm that is especially applicable, if a large number of final partitions, e.g., more than 1000, has to be c...
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| Published in: | Journal of systems architecture Vol. 49; no. 12; pp. 521 - 528 |
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01-12-2003
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| Abstract | In many application in VLSI CAD, a given netlist has to be partitioned into smaller sub-designs which can be handled much better. In this paper we present a new recursive bi-partitioning algorithm that is especially applicable, if a large number of final partitions, e.g., more than 1000, has to be computed. The algorithm consists of two steps. Based on recursive splits the problem is divided into several sub-problems, but with increasing recursion depth more run time is invested. By this an initial solution is determined very fast. The core of the method is a second step, where a very powerful greedy algorithm is applied to refine the partitions. Experimental results are given that compare the new approach to state-of-the-art tools. The experiments show that the new approach outperforms the standard techniques with respect to run time and quality. Furthermore, the memory usage is very low and is reduced in comparison to other methods by more than a factor of four. |
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| AbstractList | In many application in VLSI CAD, a given netlist has to be partitioned into smaller sub-designs which can be handled much better. In this paper we present a new recursive bi-partitioning algorithm that is especially applicable, if a large number of final partitions, e.g., more than 1000, has to be computed. The algorithm consists of two steps. Based on recursive splits the problem is divided into several sub-problems, but with increasing recursion depth more run time is invested. By this an initial solution is determined very fast. The core of the method is a second step, where a very powerful greedy algorithm is applied to refine the partitions. Experimental results are given that compare the new approach to state-of-the-art tools. The experiments show that the new approach outperforms the standard techniques with respect to run time and quality. Furthermore, the memory usage is very low and is reduced in comparison to other methods by more than a factor of four. In many application in VLSI CAD, a given netlist has to be partitioned into smaller sub-designs which can be handled much better. In this paper we present a new recursive bi-partitioning algorithm that is especially applicable, if a large number of final partitions, e.g., more than 1000, has to be computed. The algorithm consists of two steps. Based on recursive splits the problem is divided into several sub-problems, but with increasing recursion depth more run time is invested. By this an initial solution is determined very fast. The core of the method is a second step, where a very powerful greedy algorithm is applied to refine the partitions. Experimental results are given that compare the new approach to state-of-the-art tools. The experiments show that the new approach outperforms the standard techniques with respect to run time and quality. Furthermore, the memory usage is very low and is reduced in comparison to other methods by more than a factor of four. [PUBLICATION ABSTRACT] |
| Author | Günther, W. Angst, G. Linhard, L. Eschbach, T. Drechsler, R. |
| Author_xml | – sequence: 1 givenname: R. surname: Drechsler fullname: Drechsler, R. email: drechsle@informatik.uni-bremen.de organization: Institute of Computer Science, University of Bremen, 28359 Bremen, Germany – sequence: 2 givenname: W. surname: Günther fullname: Günther, W. organization: Infineon Technologies, 81730 Munich, Germany – sequence: 3 givenname: T. surname: Eschbach fullname: Eschbach, T. organization: Institute of Computer Science, Albert-Ludwigs-University, 79110 Freiburg, Germany – sequence: 4 givenname: L. surname: Linhard fullname: Linhard, L. organization: Concept Engineering GmbH, Bötzinger Strasse 29, 79111 Freiburg, Germany – sequence: 5 givenname: G. surname: Angst fullname: Angst, G. organization: Concept Engineering GmbH, Bötzinger Strasse 29, 79111 Freiburg, Germany |
| BookMark | eNqFkE9LAzEQxYNUsFU_grB40sNqZrOb3ZxE6l8oCNp7yGYnJaVNarJb8NubturV0zxmfm-GeRMyct4hIRdAb4ACv_0A1rC85gVcUXZNKRUs50dkDE2dBPBqlPQvckImMS4TVFVQjMnDO-ohRLvFrLX5RoXe9tY76xaZN5nDfmVjHzPjQ7ZSYYGZG9Ytht3wD45n5NioVcTzn3pK5k-P8-lLPnt7fp3ez3LNCtHnujMagXZcoSiZrgFE05al0oIXrTGlhgKEFqwyShtAoxQzqSdKyo3Cmp2Sy8PaTfCfA8ZeLv0QXLooC2gaUTc1JKg6QDr4GAMauQl2rcKXBCp3ccl9XHKXhaRM7uOSPPnuDj5MD2wtBhm1RaexswF1Lztv_9nwDYRRdK4 |
| Cites_doi | 10.1145/309847.309954 10.1109/DAC.1997.597203 10.21236/ADA211914 10.1109/ICCAD.1993.580083 10.1109/ICCD.2000.878309 10.1145/274535.274546 10.1109/DSD.2001.952117 10.7155/jgaa.00001 10.1109/MDT.1986.294939 10.1016/0167-9260(95)00008-4 10.1016/S0305-0548(96)00083-4 10.1109/12.8730 10.1109/DAC.1982.1585498 10.1145/266021.266275 10.1109/DSD.2001.952262 10.1002/j.1538-7305.1970.tb01770.x 10.1109/TC.1984.1676460 10.1109/12.260640 10.1016/0167-9260(91)90004-5 10.1109/DAC.1996.545551 |
| ContentType | Journal Article |
| Copyright | 2003 Elsevier B.V. Copyright Elsevier Sequoia S.A. Dec 2003 |
| Copyright_xml | – notice: 2003 Elsevier B.V. – notice: Copyright Elsevier Sequoia S.A. Dec 2003 |
| DBID | AAYXX CITATION 7SC 8FD JQ2 L7M L~C L~D |
| DOI | 10.1016/S1383-7621(03)00093-6 |
| DatabaseName | CrossRef Computer and Information Systems Abstracts Technology Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional |
| DatabaseTitle | CrossRef Computer and Information Systems Abstracts Technology Research Database Computer and Information Systems Abstracts – Academic Advanced Technologies Database with Aerospace ProQuest Computer Science Collection Computer and Information Systems Abstracts Professional |
| DatabaseTitleList | Computer and Information Systems Abstracts |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Computer Science |
| EISSN | 1873-6165 |
| EndPage | 528 |
| ExternalDocumentID | 567319661 10_1016_S1383_7621_03_00093_6 S1383762103000936 |
| Genre | Feature |
| GroupedDBID | --K --M -~X .DC .~1 0R~ 1B1 1~. 1~5 29L 4.4 457 4G. 5GY 5VS 7-5 71M 8P~ AACTN AAEDT AAEDW AAIAV AAIKJ AAKOC AALRI AAOAW AAQFI AAQXK AAXUO AAYFN ABBOA ABFNM ABFRF ABJNI ABMAC ABXDB ABYKQ ACDAQ ACGFO ACGFS ACNNM ACRLP ACZNC ADBBV ADEZE ADJOM ADMUD ADTZH AEBSH AECPX AEFWE AEKER AENEX AFKWA AFTJW AGHFR AGUBO AGYEJ AHJVU AHZHX AIALX AIEXJ AIKHN AITUG AJBFU AJOXV ALMA_UNASSIGNED_HOLDINGS AMFUW AMRAJ AOUOD ASPBG AVWKF AXJTR AZFZN BJAXD BKOJK BKOMP BLXMC CS3 DU5 EBS EFJIC EFLBG EJD EO8 EO9 EP2 EP3 FDB FEDTE FGOYB FIRID FNPLU FYGXN G-Q GBLVA GBOLZ HVGLF HZ~ IHE J1W JJJVA KOM M41 MO0 MS~ N9A O-L O9- OAUVE OZT P-8 P-9 P2P PC. PQQKQ Q38 R2- RIG ROL RPZ RXW SBC SDF SDG SDP SES SEW SPC SPCBC SST SSV SSZ T5K TAE TN5 U5U UHS ~G- AAXKI AAYXX AFJKZ AKRWK CITATION 7SC 8FD JQ2 L7M L~C L~D |
| ID | FETCH-LOGICAL-c329t-cdfce10d6ae943c71198b44ac962bff4c1219c935facf1efaa3fc129406fae73 |
| ISSN | 1383-7621 |
| IngestDate | Thu Oct 10 15:54:15 EDT 2024 Thu Sep 26 18:25:15 EDT 2024 Fri Feb 23 02:28:01 EST 2024 |
| IsDoiOpenAccess | false |
| IsOpenAccess | true |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 12 |
| Language | English |
| LinkModel | OpenURL |
| MergedId | FETCHMERGED-LOGICAL-c329t-cdfce10d6ae943c71198b44ac962bff4c1219c935facf1efaa3fc129406fae73 |
| OpenAccessLink | http://www.informatik.uni-bremen.de/agra/doc/work/dsd2002_mincut_net.pdf |
| PQID | 218897871 |
| PQPubID | 9850 |
| PageCount | 8 |
| ParticipantIDs | proquest_journals_218897871 crossref_primary_10_1016_S1383_7621_03_00093_6 elsevier_sciencedirect_doi_10_1016_S1383_7621_03_00093_6 |
| PublicationCentury | 2000 |
| PublicationDate | 2003-12-01 |
| PublicationDateYYYYMMDD | 2003-12-01 |
| PublicationDate_xml | – month: 12 year: 2003 text: 2003-12-01 day: 01 |
| PublicationDecade | 2000 |
| PublicationPlace | Amsterdam |
| PublicationPlace_xml | – name: Amsterdam |
| PublicationTitle | Journal of systems architecture |
| PublicationYear | 2003 |
| Publisher | Elsevier B.V Elsevier Sequoia S.A |
| Publisher_xml | – name: Elsevier B.V – name: Elsevier Sequoia S.A |
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| References_xml | – volume: 24 start-page: 1175 year: 1997 end-page: 1186 ident: BIB18 article-title: Arc crossing minimization in hierarchical digraphs with tabu search publication-title: Computers and Operations Research contributor: fullname: Valls – volume: 11 start-page: 11 year: 1991 end-page: 27 ident: BIB9 article-title: ASG: Automatic schematic generator publication-title: INTEGRATION, the VLSI Journal contributor: fullname: Parng – volume: volume 1731 of LNCS 1 start-page: 217 year: 1999 end-page: 224 ident: BIB19 article-title: Using sifting for publication-title: Graph Drawing Conference contributor: fullname: Molitor – volume: 38 start-page: 62 year: 1989 end-page: 81 ident: BIB20 article-title: Multiple-way network partitioning publication-title: IEEE Transactions on Computers contributor: fullname: Sanchis – start-page: 58 year: 1986 end-page: 65 ident: BIB17 article-title: Automatic generation of digital system schematic diagrams publication-title: IEEE Design & Test of Computers contributor: fullname: Misra – volume: 49 start-page: 291 year: 1970 end-page: 307 ident: BIB15 article-title: An efficient heuristic procedure for partitioning graphs publication-title: The Bell System Technical Journal contributor: fullname: Lin – volume: 1–2 start-page: 1 year: 1995 end-page: 81 ident: BIB3 article-title: Recent directions in netlist partitioning: A survey publication-title: INTEGRATION, the VLSI Journal contributor: fullname: Kahng – volume: 1 start-page: 1 year: 1997 end-page: 25 ident: BIB11 article-title: 2-layer straightline crossing minimization: Performance of exact and heuristic algorithms publication-title: Journal of the Graph and Algorithms Application contributor: fullname: Mutzel – volume: 33 start-page: 438 year: 1984 end-page: 446 ident: BIB16 article-title: An improved min-cut algorithm for partitioning VLSI networks publication-title: IEEE Transactions on Computers contributor: fullname: Krishnamurthy – volume: 42 start-page: 1500 year: 1993 end-page: 1504 ident: BIB21 article-title: Multiple-way partitioning with different cost functions publication-title: IEEE Transactions on Computers contributor: fullname: Sanchis – ident: 10.1016/S1383-7621(03)00093-6_BIB14 doi: 10.1145/309847.309954 – ident: 10.1016/S1383-7621(03)00093-6_BIB12 doi: 10.1109/DAC.1997.597203 – ident: 10.1016/S1383-7621(03)00093-6_BIB5 doi: 10.21236/ADA211914 – ident: 10.1016/S1383-7621(03)00093-6_BIB7 doi: 10.1109/ICCAD.1993.580083 – ident: 10.1016/S1383-7621(03)00093-6_BIB22 doi: 10.1109/ICCD.2000.878309 – ident: 10.1016/S1383-7621(03)00093-6_BIB1 doi: 10.1145/274535.274546 – ident: 10.1016/S1383-7621(03)00093-6_BIB4 doi: 10.1109/DSD.2001.952117 – volume: 1 start-page: 1 issue: 1 year: 1997 ident: 10.1016/S1383-7621(03)00093-6_BIB11 article-title: 2-layer straightline crossing minimization: Performance of exact and heuristic algorithms publication-title: Journal of the Graph and Algorithms Application doi: 10.7155/jgaa.00001 contributor: fullname: Jünger – start-page: 58 year: 1986 ident: 10.1016/S1383-7621(03)00093-6_BIB17 article-title: Automatic generation of digital system schematic diagrams publication-title: IEEE Design & Test of Computers doi: 10.1109/MDT.1986.294939 contributor: fullname: Kumar – volume: 1–2 start-page: 1 issue: 19 year: 1995 ident: 10.1016/S1383-7621(03)00093-6_BIB3 article-title: Recent directions in netlist partitioning: A survey publication-title: INTEGRATION, the VLSI Journal doi: 10.1016/0167-9260(95)00008-4 contributor: fullname: Alpert – volume: 24 start-page: 1175 issue: 12 year: 1997 ident: 10.1016/S1383-7621(03)00093-6_BIB18 article-title: Arc crossing minimization in hierarchical digraphs with tabu search publication-title: Computers and Operations Research doi: 10.1016/S0305-0548(96)00083-4 contributor: fullname: Laguna – volume: 38 start-page: 62 issue: 1 year: 1989 ident: 10.1016/S1383-7621(03)00093-6_BIB20 article-title: Multiple-way network partitioning publication-title: IEEE Transactions on Computers doi: 10.1109/12.8730 contributor: fullname: Sanchis – ident: 10.1016/S1383-7621(03)00093-6_BIB8 doi: 10.1109/DAC.1982.1585498 – ident: 10.1016/S1383-7621(03)00093-6_BIB2 doi: 10.1145/266021.266275 – ident: 10.1016/S1383-7621(03)00093-6_BIB13 – ident: 10.1016/S1383-7621(03)00093-6_BIB6 doi: 10.1109/DSD.2001.952262 – volume: 49 start-page: 291 issue: 1 year: 1970 ident: 10.1016/S1383-7621(03)00093-6_BIB15 article-title: An efficient heuristic procedure for partitioning graphs publication-title: The Bell System Technical Journal doi: 10.1002/j.1538-7305.1970.tb01770.x contributor: fullname: Kernighan – volume: 33 start-page: 438 issue: 5 year: 1984 ident: 10.1016/S1383-7621(03)00093-6_BIB16 article-title: An improved min-cut algorithm for partitioning VLSI networks publication-title: IEEE Transactions on Computers doi: 10.1109/TC.1984.1676460 contributor: fullname: Krishnamurthy – volume: volume 1731 of LNCS 1 start-page: 217 year: 1999 ident: 10.1016/S1383-7621(03)00093-6_BIB19 article-title: Using sifting for k-layer straightline crossing minimization contributor: fullname: Matuszewski – volume: 42 start-page: 1500 issue: 12 year: 1993 ident: 10.1016/S1383-7621(03)00093-6_BIB21 article-title: Multiple-way partitioning with different cost functions publication-title: IEEE Transactions on Computers doi: 10.1109/12.260640 contributor: fullname: Sanchis – volume: 11 start-page: 11 year: 1991 ident: 10.1016/S1383-7621(03)00093-6_BIB9 article-title: ASG: Automatic schematic generator publication-title: INTEGRATION, the VLSI Journal doi: 10.1016/0167-9260(91)90004-5 contributor: fullname: Jehng – ident: 10.1016/S1383-7621(03)00093-6_BIB10 doi: 10.1109/DAC.1996.545551 |
| SSID | ssj0005512 |
| Score | 1.6650047 |
| Snippet | In many application in VLSI CAD, a given netlist has to be partitioned into smaller sub-designs which can be handled much better. In this paper we present a... |
| SourceID | proquest crossref elsevier |
| SourceType | Aggregation Database Publisher |
| StartPage | 521 |
| SubjectTerms | Algorithms Mathematical models Studies Systems design |
| Title | Recursive bi-partitioning of netlists for large number of partitions |
| URI | https://dx.doi.org/10.1016/S1383-7621(03)00093-6 https://www.proquest.com/docview/218897871 |
| Volume | 49 |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://sdu.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwtV1Lb9QwELa27YULb0QpIB-oBFp5iWMnsY-lDSoIcaAr0ZvlOLZaqdpWZPv_Gb-SslDxkLhEu5OJI818Gc_Y4xmEXhVW00J0DeksZ4SXvSVd3TtCrW6A5Cwr_Gnk45Pm86k4ank7m-VSFRPtv2oaaKBrf3L2L7Q9DgoE-A06hytoHa5_pPcvfgE95qSfkyvPkJdcfcqGXV-AXkMNhvmFTwKfx5YgIfE5Mw-3eKyx6vMwv7n5MDrCYDnPhtxJeTGm9fiN-HeHq3WCxtfxTgthdadjI6rlSIXQ-EzHbPtPix9WJNhGdsfPR2WCZYVQmIDljXw20kTDIHaNzSKyOY4VTDPsyhvGtcoPp3_il1NAXI04Gd-37_tv7ZcyLN6QjbLbYSIPvJ4VDJ5nqrfQTgl2C8zmzsGH9vTjlDNUxe3zPPZ0JOzt9MLXBXuTXnabs7Mx7QdfZnkf3U0qxQcRPQ_QzK4eonu5wQdO9v4ROhrBhDfAhC8dzmDCACYcwIQjmPzNCUyP0fJ9uzw8JqntBjGslGtiemcsLfpaW8mZaSiVouNcG1mXnXPcUJjljGSV08ZR67RmDmgSXEOnbcOeoO3V5co-RdhI3lFT9VXpo1bb-dhe9EVfOV4XUuhdtMjiUVexuIoasw69PJWXpyqYCvJU9S4SWYgqeYjR81Og_d89upeFrtLnOijwb4WEKYs--_eB99Cd6SN4jrbX367tC7Q19NcvE3y-A2QGjaE |
| link.rule.ids | 315,782,786,27933,27934 |
| linkProvider | Elsevier |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Recursive+bi-partitioning+of+netlists+for+large+number+of+partitions&rft.jtitle=Journal+of+systems+architecture&rft.au=Drechsler%2C+R.&rft.au=G%C3%BCnther%2C+W.&rft.au=Eschbach%2C+T.&rft.au=Linhard%2C+L.&rft.date=2003-12-01&rft.pub=Elsevier+B.V&rft.issn=1383-7621&rft.eissn=1873-6165&rft.volume=49&rft.issue=12&rft.spage=521&rft.epage=528&rft_id=info:doi/10.1016%2FS1383-7621%2803%2900093-6&rft.externalDocID=S1383762103000936 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1383-7621&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1383-7621&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1383-7621&client=summon |