A multichip superconducting microcomputer ETL-JC1

• Published in: IEEE Transactions on Magnetics (Institute of Electrical and Electronics Engineers); (United States) Vol. 27; no. 2; pp. 2610 - 2617
• Main Authors: Takada, S., Nakagawa, H., Kurosawa, I., Aoyagi, M., Kosaka, S., Okada, Y., Hamazaki, Y.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01-03-1991; Institute of Electrical and Electronics Engineers
• Subjects: 240100 > Power Systems > (1990-); 990200 > Mathematics & Computers; ALUMINIUM COMPOUNDS; ALUMINIUM OXIDES; Applied sciences; CHALCOGENIDES; COMPUTER CODES; COMPUTER-AIDED DESIGN; COMPUTERS; CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY; DESIGN; Design automation; ELECTRONIC CIRCUITS; Electronics; ELEMENTS; Exact sciences and technology; FEASIBILITY STUDIES; GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; JOSEPHSON JUNCTIONS; JUNCTIONS; Large scale integration; LOGIC CIRCUITS; MEMORY MANAGEMENT; METALS; Microcomputers; MICROELECTRONIC CIRCUITS; MICROPROCESSORS; NIOBIUM; OPERATION; OXIDES; OXYGEN COMPOUNDS; PLANNING; POWER TRANSMISSION; POWER TRANSMISSION AND DISTRIBUTION; Random access memory; Read only memory; Read-write memory; Reduced instruction set computing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Superconducting devices; SUPERCONDUCTING JUNCTIONS; TRANSITION ELEMENTS 665412 > Superconducting Devices > (1992-)
• ISSN: 0018-9464; 1941-0069
• DOI: 10.1109/20.133749

A multichip 4-b superconducting microcomputer named ETL-JC1 has been designed based on Josephson LSI technology in order to demonstrate the feasibility of a Josephson computer system. The ETL-JC1 is the first Josephson computer than can execute a computer program stored in the ROM chip. In order to make the ETL-JC1, the following key technologies were developed: an Nb tunnel junction integration process, an LSI logic circuit, memory chips of 1-kb ROM and 1-kb RAM a CAD (computer-aided design) system to develop Josephson LSIs, and a multiphase power supply system. The computer consists of four Josephson LSI chips essential to execute the computer functions of arithmetic-logic, sequence control, program memory, and data memory. The whole computer system was based on a RISC (reduced-instruction-set computer) architecture. The four chips were fabricated using a 3- mu m Nb/Al-oxide/Nb junction integration process. Photomasks for the logic circuits were made by using the CAD system, in which the layout of logic gates on the chip and wiring among them were carried out using a standard-cell method. The 128-step program was executed fully in the ETL-JC1 to test a full set of 27 kinds of basic RISC instructions, memory access, subroutine call/return, and so forth, which are sufficient to make any computer program. The total power dissipation was 6.2 mW in all circuits of the ETL-JC1 consisting of more than 22000 junctions. An operation speed of 1 GIPS (giga-instruction per second) can be expected with single CPU in this system by computer logic simulation.