NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA

• Published in: Integration (Amsterdam) Vol. 63; pp. 204 - 212
• Main Authors: Hassan, Amr, Mostafa, Hassan, Fahmy, Hossam A.H.
• Format: Journal Article
• Language: English
• Published: Amsterdam Elsevier B.V 01-09-2018; Elsevier BV
• Subjects: Channels; Dynamic Partial Reconfiguration; Dynamic programming; Field Programmable Gate Arrays; Gate arrays; Integrated circuits; Network on Chip; Networks; Performance degradation; Reconfiguration; Routers; Simulation; System on chip; Network on Chip; Dynamic Partial Reconfiguration; Field Programmable Gate Arrays
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2018.04.003

Due to the ability of Dynamic Partial Reconfiguration (DPR) of SRAM-based Field Programmable Gate Arrays (FPGAs) to add more flexibility over runtime phase, DPR is attracting more interest. Recently, FPGA manufacturers are facilitating the design of applications that utilize DPR. One of the main issues in our knowledge of DPR's current techniques (i.e., ICAP and JTAG) is a performance bottleneck; only one DPR is allowed at a time. In this paper, a state-of-art NoC-based FPGA simulator which supports DPR simulation is proposed. The proposed NoC-DPR simulator is used to investigate design limitations and performance degradation of using DPR on NoC-based FPGA. To estimate the reconfiguration time overhead, which results from increasing the number of simultaneous DPRs on FPGA fabric, some experimental investigations are carried out using NoC-DPR simulator. These investigations revealed that the overhead of reconfiguration time increases exponentially with increasing the number of simultaneous DPRs. However, further investigations show that the network of wormhole routers with virtual channels optimizes the reconfiguration time with a factor up to 4x than that of the network of wormhole routers without virtual channels.
•A state-of-art NoC-DPR simulator is proposed.•Some recommendations are extracted for the implementation of DPR on NoC-based FPGA.•The optimal size of network is calculated based on reconfiguration time requirements.•The DPR of NoC-based FPGA is studied and evaluated using an embedded application.•The reconfiguration time is enhanced with factor 6.5x over the conventional SRAM-based FPGA.